74112 FLOP Datasheet

74112 Datasheet, PDF, Equivalent


Part Number

74112

Description

DUAL J-K FLIP FLOP

Manufacture

STMicroelectronics

Total Page 11 Pages
Datasheet
Download 74112 Datasheet


74112
M54HC112
M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
. HIGH SPEED
fMAX = 67 MHz (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 2 µA AT TA = 25 °C
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
|IOH| = IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS112
DESCRIPTION
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 11 2F 1R
M 74H C1 12 M1 R
M 74HC 11 2B 1R
M 74H C1 12 C1 R
The M54/74HC112 is a high speed CMOS DUAL J-K
FLIP-FLOP WITH PRESET AND CLEAR fabricated in
silicon gate C2MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS low power consumption. The
M54HC112/M74HC112 dual JK flip-flop features indi-
vidual J,K, clock, and asynchronous set and clearinputs
for each flip-flop. When the clock goes high, the inputs
are enabled and data will be accepted. The logic level
of the J and K inputs may be allowed to change when
the clock pulse is high and the bistable will function as
shown in the truth table. Input data is transferred to the
input on the negative going edge of the clock pulse. All
inputs are equipped withprotection circuits against static
discharge and transient excess voltage.
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
October 1992
NC =
No Internal
Connection
1/11

74112
M54/M74HC112
TRUTH TABLE
CLR
L
H
L
H
H
H
H
H
X: Don’t Care
PR
H
L
L
H
H
H
H
H
INPUTS
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
OUTPUTS
CK Q
Q
XLH
XH L
XHH
Qn Qn
HL
LH
Qn Qn
Qn Qn
PIN DESCRIPTION
PIN No
1, 13
2, 12
3, 11
4, 10
5, 9
6, 7
15, 14
8
16
SYMBOL
1CK, 2CK
1K, 2K
1J, 2J
1PR, 2PR
1Q, 2Q
1Q, 2Q
1CLR,
2CLR
GND
VCC
NAME AND FUNCTION
Clock Input (HIGH to
LOW edge triggered)
Data Inputs: Flip-Flop 1
and 2
Data Inputs: Flip-Flop 1
and 2
Set Inputs
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
Reset inputs
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOL
LOGIC DIAGRAM (1/2 Package)
FUNCTION
CLEAR
PRESET
NO CHANGE
TOGGLE
NO CHANGE
2/11


Features M54HC112 M74HC112 DUAL J-K FLIP FLOP WIT H PRESET AND CLEAR . . . . . . . . HI GH SPEED fMAX = 67 MHz (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 2 µA A T TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE C APABILITY 10 LSTTL LOADS SYMMETRICAL OU TPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN. ) BALANCED PROPAGATION DELAYS tPLH = tP HL WIDE OPERATING VOLTAGE RANGE VCC (OP R) = 2 V TO 6 V PIN AND FUNCTION COMPAT IBLE WITH 54/74LS112 B1R (Plastic Pack age) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) ORDER CO DES : M54HC112F1R M74HC112M1R M74HC112B 1R M74HC112C1R DESCRIPTION The M54/74H C112 is a high speed CMOS DUAL J-K FLIP -FLOP WITH PRESET AND CLEAR fabricated in silicon gate C2MOS technology. It ha s the same high speed performance of LS TTL combined with true CMOS low power c onsumption. The M54HC112/M74HC112 dual JK flip-flop features individual J,K, c lock, and asynchronous set and clearinp uts for each flip-flop. When the clock goes high, the inputs are .
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