74138 Decoder/Demultiplexer Datasheet

74138 Datasheet, PDF, Equivalent


Part Number

74138

Description

Decoder/Demultiplexer

Manufacture

Fairchild Semiconductor

Total Page 7 Pages
Datasheet
Download 74138 Datasheet


74138
August 1986
Revised March 2000
DM74LS138 • DM74LS139
Decoder/Demultiplexer
General Description
These Schottky-clamped circuits are designed to be used
in high-performance memory-decoding or data-routing
applications, requiring very short propagation delay times.
In high-performance memory systems these decoders can
be used to minimize the effects of system decoding. When
used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of
the memory. This means that the effective system delay
introduced by the decoder is negligible.
The DM74LS138 decodes one-of-eight lines, based upon
the conditions at the three binary select inputs and the
three enable inputs. Two active-low and one active-high
enable inputs reduce the need for external gates or invert-
ers when expanding. A 24-line decoder can be imple-
mented with no external inverters, and a 32-line decoder
requires only one inverter. An enable input can be used as
a data input for demultiplexing applications.
The DM74LS139 comprises two separate two-line-to-four-
line decoders in a single package. The active-low enable
input can be used as a data line in demultiplexing applica-
tions.
All of these decoders/demultiplexers feature fully buffered
inputs, presenting only one normalized load to its driving
circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify sys-
tem design.
Features
s Designed specifically for high speed:
Memory decoders
Data transmission systems
s DM74LS138 3-to-8-line decoders incorporates 3 enable
inputs to simplify cascading and/or data reception
s DM74LS139 contains two fully independent 2-to-4-line
decoders/demultiplexers
s Schottky clamped for high performance
s Typical propagation delay (3 levels of logic)
DM74LS138 21 ns
DM74LS139 21 ns
s Typical power dissipation
DM74LS138 32 mW
DM74LS139 34 mW
Ordering Code:
Order Number Package Number
Package Description
DM74LS138M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS138SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS138N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS139M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS139SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS139N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006391
www.fairchildsemi.com

74138
Connection Diagrams
DM74LS138
DM74LS139
Function Tables
DM74LS138
DM74LS139
Inputs
Enable
Select
Outputs
Inputs
Enable
Select
Outputs
G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7
G B A Y0 Y1 Y2
X H XXX H H H H H H H H
H
XX
H
H
H
L X XXX H H H H H H H H
L
LL
L
H
H
H L LLL L H H H H H H H
L
LH
H
L
H
H L LLH H L H H H H H H
L
HL
H
H
L
H L LHL H H L H H H H H
L
HH
H
H
H
H L LHH H H H L H H H H
H L HLL H H H H L H H H
H L H L H H H H H H L H H H = HIGH Level
H
L
HH L H
HHHHH L H
L = LOW Level
X = Don’t Care
H L HHH H H H H H H H L
Note 1: G2 = G2A + G2B
Y3
H
H
H
H
L
Logic Diagrams
DM74LS138
DM74LS139
www.fairchildsemi.com
2


Features DM74LS138 • DM74LS139 Decoder/Demultip lexer August 1986 Revised March 2000 DM74LS138 • DM74LS139 Decoder/Demulti plexer General Description These Schott ky-clamped circuits are designed to be used in high-performance memory-decodin g or data-routing applications, requiri ng very short propagation delay times. In high-performance memory systems thes e decoders can be used to minimize the effects of system decoding. When used w ith high-speed memories, the delay time s of these decoders are usually less th an the typical access time of the memor y. This means that the effective system delay introduced by the decoder is neg ligible. The DM74LS138 decodes one-of-e ight lines, based upon the conditions a t the three binary select inputs and th e three enable inputs. Two active-low a nd one active-high enable inputs reduce the need for external gates or inverte rs when expanding. A 24-line decoder ca n be implemented with no external inver ters, and a 32-line decoder requires only one inverter. An enable i.
Keywords 74138, datasheet, pdf, Fairchild Semiconductor, Decoder/Demultiplexer, 4138, 138, 38, 7413, 741, 74, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




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