74173 Reset Datasheet

74173 Datasheet, PDF, Equivalent


Part Number

74173

Description

Quad 3-State D Flip-Flop with Common Clock and Reset

Manufacture

Motorola Inc

Total Page 6 Pages
Datasheet
Download 74173 Datasheet


74173
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173 to be used in bus–oriented systems. The Reset feature is
asynchronous and active high.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 208 FETs or 52 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0 14
D1 13
D2 12
D3 11
3 Q0
4 Q1
5 Q2
6 Q3
3–STATE
NONINVERTING
OUTPUTS
CLOCK 7
MC74HC173
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
OE1
OE2
Q0
Q1
Q2
Q3
CLOCK
GND
1
2
3
4
5
6
7
8
16 VCC
15 RESET
14 D0
13 D1
12 D2
11 D3
10 DE2
9 DE1
DATA–
ENABLES
DE1 9
DE2 10
RESET 15
OUTPUT OE1 1
ENABLES OE2 2
VCC = PIN 16
GND = PIN 8
Output Enables
OE1 OE2
LL
LL
LL
LL
LL
LL
LL
LL
LH
HL
HH
Reset
H
L
L
L
L
L
L
L
X
X
X
FUNCTION TABLE
Inputs
Data Enables
Clock DE1 DE2
XXX
LXX
HXX
HX
XH
LL
LL
XX
XXX
XXX
XXX
Output
Data
D
X
X
X
X
X
L
H
X
X
X
X
Q
L
No Change
No Change
No Change
No Change
L
H
No Change
High Impedance
High Impedance
High Impedance
10/95
© Motorola, Inc. 1995
1 REV 6

74173
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMC74HC173
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIout
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 1.5 to VCC + 1.5
– 0.5 to VCC + 0.5
± 20
DC Output Current, per Pin
± 35
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
± 75
750
500
V
V
V
mA
mA
mA
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Plastic DIP or SOIC Package)
– 65 to + 150
260
_C
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* Maximum Ratings are those values beyond which damage to the device may occur.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
v vVout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎRECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Min Max Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC DC Supply Voltage (Referenced to GND)
2.0 6.0 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin, Vout DC Input Voltage, Output Voltage (Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature, All Package Types
0 VCC
– 55 + 125
V
_C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise and Fall Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
v v– 55 to
25_C
85_C
125_C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIH Minimum High–Level Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 1.5 1.5 1.5
4.5 3.15 3.15 3.15
6.0 4.2 4.2 4.2
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIL Maximum Low–Level Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVoltage
vVout = 0.1 V or VCC – 0.1 V
|Iout| 20 µA
2.0 0.3 0.3 0.3 V
4.5 0.9 0.9 0.9
6.0 1.2 1.2 1.2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOH
Minimum High–Level Output
Voltage
vVin = VIH or VIL
|Iout| 20 µA
vVin = VIH or VIL |Iout| 6.0 mA
v|Iout| 7.8 mA
2.0
4.5
6.0
4.5
6.0
1.9
4.4
5.9
3.98
5.48
1.9 1.9
4.4 4.4
5.9 5.9
3.84 3.70
5.34 5.20
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIOZ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC
Maximum Low–Level Output
Voltage
vVin = VIH or VIL
|Iout| 20 µA
Maximum Input Leakage Current
Maximum Three–State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
vVin = VIH or VIL |Iout| 6.0 mA
v|Iout| 7.8 mA
Vin = VCC or GND
Output in High–Impedance State
Vin = VIL or VIH
Vout = VCC or GND
Vin = VCC or GND
Iout = 0 µA
2.0
4.5
6.0
4.5
6.0
6.0
6.0
6.0
0.1
0.1
0.1
0.26
0.26
± 0.1
± 0.5
8
0.1
0.1
0.1
0.33
0.33
± 1.0
± 5.0
80
0.1
0.1
0.1
0.40
0.40
± 1.0
± 10
160
V
µA
µA
µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
MOTOROLA
2 High–Speed CMOS Logic Data
DL129 — Rev 6


Features MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 3-State D Flip-Flop with Common Cl ock and Reset High–Performance Silico n–Gate CMOS The MC74HC173 is identica l in pinout to the LS173. The device in puts are compatible with standard CMOS outputs; with pullup resistors, they ar e compatible with LSTTL outputs. Data, when enabled, are clocked into the four D flip–flops with the rising edge of the common Clock. When either or both of the Output Enable Controls is high, the outputs are in a high–impedance s tate. This feature allows the HC173 to be used in bus–oriented systems. The Reset feature is asynchronous and activ e high. • • • • • • Output Drive Capability: 15 LSTTL Loads Output s Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 µA High Noise Imm unity Characteristic of CMOS Devices In Compliance with the Requirements Defin ed by JEDEC Standard No. 7A • Chip Co mplexity 208 FETs or 52 Equivalent Gates LOGIC DIAGRAM D0 14 D1 13 D2 12 D3 11 3 Q0 4 Q1.
Keywords 74173, datasheet, pdf, Motorola Inc, Quad, 3-State, D, Flip-Flop, with, Common, Clock, and, Reset, 4173, 173, 73, 7417, 741, 74, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)