74194 REGISTER Datasheet

74194 Datasheet, PDF, Equivalent


Part Number

74194

Description

4 BIT PIPO SHIFT REGISTER

Manufacture

STMicroelectronics

Total Page 12 Pages
Datasheet
Download 74194 Datasheet


74194
M54HC194
M74HC194
. HIGH SPEED
tPD = 12 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT TA = 25 °C
. OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
. SYMMETRICAL OUTPUT IMPEDANCE
IOH= IOL = 4 mA (MIN.)
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. HIGH NOISE IMMUNITY
VNIH = VNIL = 28 % VCC (MIN.)
. WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS194
4 BIT PIPO SHIFT REGISTER
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M 54HC 19 4F 1R
M 74H C1 94 M1 R
M 74HC 19 4B 1R
M 74H C1 94 C1 R
DESCRIPTION
The M54/74HC194 is a high speed CMOS 4 BIT PIPO
SHIFT REGISTER fabricated in silicon gate C2MOS
technology. It has the same high speed performance
of LSTTL combined with true CMOS low power con-
sumption. This SHIFT REGISTER is designed to in-
corporate virtually all of the features a system designer
may want in a shift register. It features parallel inputs,
parallel outputs, right shift and left shift serial inputs,
clear line. The register has four distinct modes of oper-
ation : PARALLEL (broadside) LOAD ; SHIFT RIGHT
(in the direction QA QD); SHIFT LEFT ; INHIBIT
CLOCK (do nothing). Synchronous parallel loading is
accomplished by applying the four data bits and taking
both mode control inputs, S0 and S1 high. The data
are loaded into their respective flip-flops and appear
at the outputs after the positive transition of the
CLOCK input. During loading, serial data flow is in-
hibited. Shift right is accomplished synchronously with
the rising edge of the clock pulse when S0 is high and
S1 is low. Serial data for this mode is entered at the
SHIFT RIGHT data input. When S0 is low and S1 is
high,data shifts left synchronously and new data is en-
tered at the SHIFT LEFT serial input. Clocking of the
flipflops is inhibited when both mode control inputs are
low. The mode control inputs should be changed only
when the CLOCK input is high. All inputs are equipped
with protection circuits against static discharge and
transient excess voltage.
October 1992
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
1/12

74194
M54/M74HC194
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
1
SYMBOL
CLEAR
2 SR
3, 4, 5, 6
7
A to D
SL
9, 10
11
S0, S1
CLOCK
15, 14, 13, 12
8
16
QA to QD
GND
VCC
NAME AND FUNCTION
Asynchronous Reset
Input (Active LOW)
Serial Data Input (Shift
Right)
Parallel Data Input
Serial Data Input (Shift
Left)
Mode Control Inputs
Clock Input (LOW to
HIGH Edge-triggered)
Paralle Outputs
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOL
TRUTH TABLE
INPUTS
CLEAR
MODE
S1 S0
CLOCK
SERIAL
PARALLEL
LEFT RIGHT A B C D
QA
L X X X X X XXXX L
HXX
X X X X X X QA0
HHH
X X abcd a
HLH
X H XXXX H
HLH
X L XXXX L
HHL
H X X X X X QBn
HHL
L X X X X X QBn
H L L X X X X X X X QA0
X: Don’t Care
a ~d
QA0 ~ QD0
QAn ~ QDn
: Don’t Care
: The level of steady state input voltage at input A ~ D respactively
: No change
: The level of QA, QB, QC, respectively, before the mst recent positive transition of the clock.
OUTPUS
QB QC
L
QB0
b
QAn
QAn
QCn
QCn
QB0
L
QC0
c
QBn
QBn
QDn
QDn
QC0
QD
L
QD0
d
QCn
QCn
H
L
QD0
2/12


Features M54HC194 M74HC194 4 BIT PIPO SHIFT REGIS TER . . . . . . . . HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V LOW POWER DIS SIPATION ICC = 4 µA (MAX.) AT TA = 25 °C OUTPUT DRIVE CAPABILITY 10 LSTTL LO ADS SYMMETRICAL OUTPUT IMPEDANCE IOH  = IOL = 4 mA (MIN.) BALANCED PROPAG ATION DELAYS tPLH = tPHL HIGH NOISE IMM UNITY VNIH = VNIL = 28 % VCC (MIN.) WID E OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V PIN AND FUNCTION COMPATIBLE W ITH 54/74LS194 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Packa ge) C1R (Chip Carrier) ORDER CODES : M54HC194F1R M74HC194M1R M74HC194B1R M74 HC194C1R DESCRIPTION The M54/74HC194 i s a high speed CMOS 4 BIT PIPO 2 SHIFT REGISTER fabricated in silicon gate C M OS technology. It has the same high spe ed performance of LSTTL combined with t rue CMOS low power consumption. This SH IFT REGISTER is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left .
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