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IDT72104 Dataheets PDF



Part Number IDT72104
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description CMOS PARALLEL-SERIAL FIFO
Datasheet IDT72104 DatasheetIDT72104 Datasheet (PDF)

CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 Integrated Device Technology, Inc. IDT72103 IDT72104 FEATURES: • 35ns parallel port access time, 45ns cycle time • 50MHz serial input/output frequency • Serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel operations • Expandable in both depth and width with no external components • Flexishift™ — Sets programmable serial word width from 4 bits to any width with no external components • Multiple flags: Full, Almost-Full .

  IDT72104   IDT72104


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CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 Integrated Device Technology, Inc. IDT72103 IDT72104 FEATURES: • 35ns parallel port access time, 45ns cycle time • 50MHz serial input/output frequency • Serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel operations • Expandable in both depth and width with no external components • Flexishift™ — Sets programmable serial word width from 4 bits to any width with no external components • Multiple flags: Full, Almost-Full (Full-1/8),Full-MinusOne, Empty, Almost-Empty (Empty + 1/8), Empty-Plus One, and Half-Full • Asynchronous and simultaneous read or write operations • Dual-Port, zero fall-through time architecture • Retransmit capability in single-device mode • Packaged in 44-pin PLCC • Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications APPLICATIONS: • • • • • • • • • High-speed data acquisition systems Local area network (LAN) buffer High-speed modem data buffer Remote telemetry data buffer FAX raster video data buffer Laser printer engine data buffer High-speed parallel bus-to-bus communications Magnetic media controllers Serial link buffer DESCRIPTION: The IDT72103/72104 are high-speed Parallel-Serial FlFOs to be used with high-performance systems for functions such as serial communications, laser printer engine control and local area networks. A serial input, a serial output and two 9-bit parallel ports make four modes of data transfer possible: serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel. The IDT72103/72104 are expandable in both depth and width for all of these operational configurations. FUNCTIONAL BLOCK DIAGRAM SERIAL INPUT SI SIX SICP DATA INPUTS (D 0 -D 8 ) SERIAL INPUT CIRCUITRY FLAG LOGIC SERIAL/ PARALLEL CONTROL RAM ARRAY 2048 x 9 4096 x 9 SI/PI SO/PO W XI XO FL/RT FF FF-1 EF+1 EF AEF HF R RS WRITE POINTER READ POINTER DEPTH EXPANSION LOGIC RESET LOGIC OE DATA OUTPUTS (Q 0 -Q 8 ) The IDT logo is a registered trademark of Integrated Device Technology,Inc. SERIAL OUTPUT CIRCUITRY SERIAL OUTPUT SO SOX SOCP 2753 drw 01 COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. DECEMBER 1996 DSC-2753/8 5.37 1 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) The IDT72103/72104 may be configured to handle serial word widths of four or greater using IDT’s unique Flexishift feature. Flexishift allows serial width and depth expansion without external components. For example, you may configure a 4K x 24 FIFO using three IDT72104s in a serial width expansion configuration. Seven flags are provided to signal memory status of the FIFO. The flags are FF (Full), AF (7/8 full), FF–1 (Full-minusone), EF (Empty), AE (1/8 full), EF+1 (Empty-plus-one), and HF (Half-full). Read (R) and Write (W) control pins are provided for asynchronous and simultaneous operations. An output enable (OE) control pin is available on the parallel output port for high-impedance control. The depth expansion control pins XO and Xl are provided to allow cascading for deeper FlFOs. The IDT72103/72104 are manufactured using IDT’s CMOS technology. PIN CONFIGURATIONS INDEX D0 XI SO/PO SOX SOCP SO AEF FF-1 FF Q0 GND GND D1 D2 D3 D4 W VCC D5 D6 D7 D8 6 7 8 9 10 11 12 13 14 15 16 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 J44-1 17 29 18 19 20 21 22 23 24 25 26 27 28 GND FL/RT RS SI SICP SIX SI/PI OE EF+1 EF XO/HF Q1 Q2 Q3 Q4 GND R Q5 Q6 Q7 Q8 GND PLCC TOP VIEW 5.37 2753 drw 03 2 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TA TBIAS TSTG IOUT Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial –0.5 to +7.0 0 to +70 –55 to +125 –55 to +125 50 Unit V °C °C °C mA 2753 tbl 01 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF 2753 tbl 02 NOTE: 1. This parameter is sampled and not 100% tested. RECOMMENDED DC OPERATING CONDITIONS Symbol VCCC GND VIH VIL(1) Parameter Commercial Supply Voltage Supply Voltage Input High Voltage Commercial Input Low Voltage Min. 4.5 0 2.0 — Typ. 5.0 0 — — Max. Unit 5.5 0 — 0.8 V V V V 2753 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. PIN DESCR.


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