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IDT72105 Dataheets PDF



Part Number IDT72105
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description CMOS PARALLEL-TO-SERIAL FIFO
Datasheet IDT72105 DatasheetIDT72105 Datasheet (PDF)

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 Integrated Device Technology, Inc. IDT72105 IDT72115 IDT72125 FEATURES: • • • • • • • • • 25ns parallel port access time, 35ns cycle time 45MHz serial output shift rate Wide x16 organization offering easy expansion Low power consumption (50mA typical) Least/Most Significant Bit first read selected by asserting the FL/DIR pin Four memory status flags: Empty, Full, Half-Full, and Almost-Empty/Almost-Full Dual-Port zero fall-through archi.

  IDT72105   IDT72105


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CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16 Integrated Device Technology, Inc. IDT72105 IDT72115 IDT72125 FEATURES: • • • • • • • • • 25ns parallel port access time, 35ns cycle time 45MHz serial output shift rate Wide x16 organization offering easy expansion Low power consumption (50mA typical) Least/Most Significant Bit first read selected by asserting the FL/DIR pin Four memory status flags: Empty, Full, Half-Full, and Almost-Empty/Almost-Full Dual-Port zero fall-through architecture Available in 28-pin 300 mil plastic DIP and 28-pin SOIC Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications DESCRIPTION: The IDT72105/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, Full, Half-Full and Almost-Empty/AlmostFull. The Full and Empty flags prevent any FIFO data overflow or underflow conditions. The Half-Full Flag is available in both single and expansion mode configurations. The Almost-Empty/ Almost-Full Flag is available only in a single device mode. The IDT72105/15/25 are fabricated using IDT’s leading edge, submicron CMOS technology. Military grade product is manufactured in compliance with the latest revision of MilSTD-883, Class B. FUNCTIONAL BLOCK DIAGRAM RS W D 0–15 16 RESET LOGIC WRITE POINTER RAM ARRAY 256 x 16 512 x 16 1024 x 16 READ POINTER RSIX RSOX FL/DIR SERIAL OUTPUT LOGIC EXPANSION LOGIC FLAG LOGIC FF EF HF AEF The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. SOCP SO 2665 drw 01 COMMERCIAL TEMPERATURE RANGE ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. DECEMBER 1996 DSC-2665/6 5.35 1 IDT72105, IDT72115, IDT72125, 256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION W D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P28-2 SO28-3 EF FF HF Vcc D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 RS RSIX GND SO SOCP RSOX/AEF FL/DIR 2665 drw 02a DIP/SOIC TOP VIEW PIN DESCRIPTIONS Symbol D0–D15 Name Inputs Reset I/O I I Data inputs for 16-bit wide data. When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. FF and HF go HIGH. EF and AEF go LOW. A reset is required before an initial WRITE after power-up. W must be high during the RS cycle. Also the First Load pin (FL) is programmed only during Reset. A write cycle is initiated on the falling edge of WRITE if the Full Flag (FF) is not set. Data set-up and hold times must be adhered to with respect to the rising edge of WRITE. Data is stored in the RAM array sequentially and independently of any ongoing read operation. A serial bit read cycle is initiated on the rising edge of SOCP if the Empty Flag (EF) is not set. In both Depth and Serial Word Width Expansion modes, all of the SOCP pins are tied together. This is a dual purpose input used in the width and depth expansion configurations. The First Load ( FL) function is programmed only during Reset (RS ) and a LOW on FL indicates the first device to be loaded with a byte of data. All other devices should be programmed HIGH. The Direction (DIR) pin controls shift direction after Reset and tells the device whether to read out the Least Significant or Most Significant bit first. In the single device configuration, RSIX is set HIGH. In depth expansion or daisy chain expansion, RSIX is connected to RSOX (expansion out) of the previous device. Serial data is output on the Serial Output (SO) pin. Data is clocked out LSB or MSB depending on the Direction pin programming. During Expansion the SO pins are tied together. When FF goes LOW, the device is full and further WRITE operations are inhibited. When HIGH, the device is not full. When EF goes LOW, the device is empty and further READ operations are inhibited. When HIGH, the device is not empty. Description RS W SOCP Write I Serial Output Clock First Load/ Direction I I FL/DIR RSIX SO Read Serial In Expansion Serial Output Full Flag Empty Flag Half-Full Flag I O O O O O FF EF HF FF is EF is When HF is LOW, the device is.


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