IDT72231 FIFO memories Datasheet

IDT72231 Datasheet, PDF, Equivalent


Part Number

IDT72231

Description

FIFO memories

Manufacture

Integrated Device Technology

Total Page 14 Pages
Datasheet
Download IDT72231 Datasheet


IDT72231
CMOS SyncFIFO
IDT72421, IDT72201
64 x 9, 256 x 9, 512 x 9,
IDT72211, IDT72221
1,024 x 9, 2,048 x 9,
IDT72231, IDT72241
4,096 x 9 and 8,192 x 9
IDT72251
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
64 x 9-bit organization (IDT72421)
256 x 9-bit organization (IDT72201)
512 x 9-bit organization (IDT72211)
1,024 x 9-bit organization (IDT72221)
2,048 x 9-bit organization (IDT72231)
4,096 x 9-bit organization (IDT72241)
8,192 x 9-bit organization (IDT72251)
10 ns read/write cycle time
Read and Write Clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set
to any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in the 32-pin plastic leaded chip carrier (PLCC) and
32-pin Thin Quad Flat Pack (TQFP)
For through-hole product please see the IDT72420/72200/72210/
72220/72230/72240 data sheet
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. These devices have a 64, 256, 512, 1,024,
2,048, 4,096, and 8,192 x 9-bit memory array, respectively. These FIFOs are
applicable for a wide variety of data buffering needs such as graphics, local area
networks and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and two write enable pins (WEN1, WEN2).
Data is written into the Synchronous FIFO on every rising clock edge when
the write enable pins are asserted. The output port is controlled by another clock
pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An output enable pin
(OE) is provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the load pin (LD).
TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0 - D8
WEN1
WEN2
LD
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
EF
PAE
PAF
FF
OUTPUT REGISTER
RESET LOGIC
RS
OE
Q0 - Q8
RCLK
REN1
REN2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncFIFO is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2655 drw01
NOVEMBER 2017
DSC-2655/7

IDT72231
IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™
64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
PIN CONFIGURATION
INDEX
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
2655 drw 02
TQFP (PR32-1, order code: PF)
TOP VIEW
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
INDEX
D1
D0
PAF
PAE
GND
REN1
RCLK
REN2
OE
4 3 2 32 31 30
5 1 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
2655 drw02a
PLCC (J32-1, order code: J)
TOP VIEW
PIN DESCRIPTIONS
Symbol
Name
D0-D8 DataInputs
RS Reset
WCLK
WEN1
Write Clock
Write Enable 1
WEN2/ Write Enable 2/
LD Load
Q0-Q8
RCLK
REN1
Data Outputs
Read Clock
Read Enable 1
REN2 Read Enable 2
OE OutputEnable
EF Empty Flag
PAE Programmable
Almost-Empty Flag
PAF Programmable
Almost-Full Flag
FF Full Flag
VCC Power
GND Ground
I/O Description
I Data inputs for a 9-bit bus.
I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable(s) are asserted.
I If the FIFO is configured to have programmable flags, WEN1 is the only write enable pin. When WEN1 is LOW,
data is written into the FIFO on every LOW-to-HIGH transition WCLK. If the FIFO is configured to have two write
enables, WEN1 must be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW.
I The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH
at reset, this pin operates as a second write enable. If WEN2/LD is LOW at reset, this pin operates as a control
to load and read the programmable flag offsets. If the FIFO is configured to have two write enables, WEN1 must
be LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO if the FF is
LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW to write or read the
programmable flag offsets.
O Data outputs for a 9-bit bus.
I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
I When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
O When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is Empty+7. PAE is synchronized to RCLK.
O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is Full-7. PAF is synchronized to WCLK.
O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
©2


Features IDT72421/72201/72211/72221/72231/72241 C MOS SyncFIFO™ 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9 CMO S SyncFIFO™ 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9 MILIT ARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. IDT 72421 IDT72201 IDT72211 IDT72221 IDT722 31 IDT72241 FEATURES: • • • • • • • • • • • • • • • • • • 64 x 9-bit organizatio n (IDT72421) 256 x 9-bit organization ( IDT72201) 512 x 9-bit organization (IDT 72211) 1024 x 9-bit organization (IDT72 221) 2048 x 9-bit organization (IDT7223 1) 4096 x 9-bit organization (IDT72241) 12 ns read/write cycle time (IDT72421/ 72201/72211) 15 ns read/write cycle tim e (IDT72221/72231/72241) Read and write clocks can be independent Dual-Ported zero fall-through time architecture Emp ty and Full flags signal FIFO status Pr ogrammable Almost-Empty and Almost-Full flags can be set to any depth Programm able Almost-Empty and Almost-Full flags default to Empty+7, and Full-7, respectively Output enable puts.
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