IDT72V16320

3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY IDT72V15160 IDT72V16160 IDT72V17160 IDT72V18160 IDT72V19160 IDT72V14320 IDT72V15320 IDT72V16320 IDT72V17320 IDT72V18320 IDT72V19320 FEATURES: Choose among the following memory organizations: Commercial V-III Vx-III IDT72V15160 - 4,096 x 16 IDT72V16160 - 8,192 x 16 IDT72V17160 - 16,384 x 16 IDT72V18160 - 32,768 x 16 IDT72V19160 - 65,536 x 16 IDT72V14320 - 1,024 x 32 IDT72V15320 - 2,048 x 32 IDT72V16320 - 4,096 x 32 IDT72V17320 - 8,192 x 32 IDT72V18320 - 16,384 x 32 IDT72V19320 - 32,768 x 32 Up to 100 MHz Operation of the Clocks 5V input tolerant Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags through serial input Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function (PBGA Only) Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III) Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid Array (PBGA) (with additional features) Industrial temperature range (–40°C to +85°C) High-performance submicron CMOS technology FUNCTIONAL BLOCK DIAGRAM *Available on the Vx-III PBGA package only. MRS WCLK WEN PRS RCLK REN OE D0 -...