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IDT72V18160 Dataheets PDF



Part Number IDT72V18160
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY
Datasheet IDT72V18160 DatasheetIDT72V18160 Datasheet (PDF)

3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY IDT72V15160 IDT72V16160 IDT72V17160 IDT72V18160 IDT72V19160 IDT72V14320 IDT72V15320 IDT72V16320 IDT72V17320 IDT72V18320 IDT72V19320 FEATURES: • Choose among the following memory organizations: Commercial V-III Vx-III • • • • • • • • IDT72V15160 - 4,096 x 16 IDT72V16160 - 8,192 x 16 IDT72V17160 - 16,384 x 16 IDT72V18160 - 32,768 x 16 IDT72V19160 - 65,536 x 16 IDT72V14320 - 1,024 x 32 IDT72V15320 - 2,048 x 32 IDT72V1.

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3.3V MULTIMEDIA FIFO 16 BIT V-III, 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY IDT72V15160 IDT72V16160 IDT72V17160 IDT72V18160 IDT72V19160 IDT72V14320 IDT72V15320 IDT72V16320 IDT72V17320 IDT72V18320 IDT72V19320 FEATURES: • Choose among the following memory organizations: Commercial V-III Vx-III • • • • • • • • IDT72V15160 - 4,096 x 16 IDT72V16160 - 8,192 x 16 IDT72V17160 - 16,384 x 16 IDT72V18160 - 32,768 x 16 IDT72V19160 - 65,536 x 16 IDT72V14320 - 1,024 x 32 IDT72V15320 - 2,048 x 32 IDT72V16320 - 4,096 x 32 IDT72V17320 - 8,192 x 32 IDT72V18320 - 16,384 x 32 IDT72V19320 - 32,768 x 32 • • • Up to 100 MHz Operation of the Clocks 5V input tolerant Auto power down minimizes standby power consumption • • Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags through serial input Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function (PBGA Only) Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III) Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid Array (PBGA) (with additional features) Industrial temperature range (–40°C to +85°C) High-performance submicron CMOS technology FUNCTIONAL BLOCK DIAGRAM *Available on the Vx-III PBGA package only. MRS WCLK WEN PRS RCLK REN OE D0 - Dn Data In x16, x32 FIFO ARRAY Q0 - Qn Data Out x16, x32 WRITE CONTROL RESET LOGIC READ CONTROL * * ** * TCK TRST TMS TDI TDO JTAG CONTROL (BOUNDARY SCAN) * LD SEN SI PFM FLAG LOGIC FSEL1 EF FSEL0 HF PAE FF PAF 6163 drw01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE 1  2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NOVEMBER 2003 DSC-6163/2 IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO INDUSTRIAL TEMPERATURE RANGE DESCRIPTION: The IDT V-III and Vx-III Multimedia FIFOs are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with independent clocked read and write controls and high density offerings up to 1 Mbit. Each FIFO has a data input port (Dn) and a data output port (Qn). The frequencies of both the RCLK (read port clock) and the WCLK (write port clock) signals may vary from 0 to f S(MAX) with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. These FIFOs have five flag pins, EF (Empty Flag), FF (Full Flag), HF (Halffull Flag), PAE (Programmable Almost-Empty flag) and PAF (Programmable Almost-Full flag). PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded with the serial interface to any user desired value or by default values. Eight default offset settings are provided, so that PAE can be set to switch at a predefined number of locations from the empty boundary and the PAF threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of WCLK, are used to load the offset registers via the Serial Input (SI). During Master Reset (MRS) the read and write pointers are set to the first location of the FIFO. PIN CONFIGURATIONS (16-BIT V-III FAMILY) WCLK PRS MRS LD SI FF PAF GND FSEL0 HF FSEL1 GND GND VCC PAE PFM EF GND RCLK REN 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 WEN SEN DNC(1) VCC DNC(1) GND GND D0 VCC D1 GND D2 D3 GND D4 D5 D6 D7 D8 VCC INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VCC OE VCC Q0 Q1 GND GND DNC(1) Q2 VCC Q3 Q4 GND Q5 GND Q6 VCC Q7 Q8 Q9 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 6163 drw02 NOTE: 1. DNC = Do Not Connect. D9 GND GND D10 D11 D12 D13 D14 D15 GND Q15 Q14 GND Q13 Q12 VCC Q11 Q10 GND DNC(1) TQFP (PN80-1, order code: PF) TOP VIEW 2 IDT72V15160/16160/17160/18160/19160 - 3.3V 16-BIT V-III MULTIMEDIA FIFO IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO INDUSTRIAL TEMPERATURE RANGE The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the programmable flag settings existing before Partial Reset remain unchanged. PRS is useful for resetting a device in midoperation, when reprogramming programmable flags would be undesirable. It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing modes can be se.


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