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IDT70V7519S Dataheets PDF



Part Number IDT70V7519S
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
Datasheet IDT70V7519S DatasheetIDT70V7519S Datasheet (PDF)

HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: x IDT70V7519S x x x x x x 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip Bank access controlled via bank address pins High-speed data access – Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through outpu.

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HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE Features: x IDT70V7519S x x x x x x 256K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture – 64 independent 4K x 36 banks – 9 megabits of memory on chip Bank access controlled via bank address pins High-speed data access – Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns (133MHz) (max.) – Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports – 5ns cycle time, 200MHz operation (14Gbps bandwidth) – Fast 3.4ns clock to data out x x x x x x – 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1 Functional Block Diagram PL/FTL OPTL CLKL ADSL CNTENL REPEATL R/WL CE0L CE1L BE3L BE2L BE1L BE0L OEL PL/FTR OPTR CLKR ADSR CNTENR REPEATR R/WR CE0R CE1R BE3R BE2R BE1R BE0R OER CONTROL LOGIC MUX 4Kx36 MEMORY ARRAY (BANK 0) MUX CONTROL LOGIC I/O0L-35L I/O CONTROL MUX 4Kx36 MEMORY ARRAY (BANK 1) MUX I/O CONTROL I/O0R-35R A11L A0L BA5L BA4L BA3L BA2L BA1L BA0L ADDRESS DECODE ADDRESS DECODE A11R A0R BA5R BA4R BA3R BA2R BA1R BA0R BANK DECODE MUX 4Kx36 MEMORY ARRAY (BANK 63) BANK DECODE NOTE: 1. The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details. MUX , TDI TDO JTAG TMS TCK TRST 5618 drw 01 DECEMBER 2002 1 DSC 5618/5 ©2002 Integrated Device Technology, Inc. IDT70V7519S High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70V7519 is a high-speed 256Kx36 (9Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 4Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 4Kx36 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7519 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion. The 70V7519 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19. Pin Configuration(1,2,3,4) 01/11/02 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 IO19L IO18L B1 B2 VSS B3 TDO B4 NC B5 BA4L B6 BA0L B7 A8L B8 BE1L B9 VDD B10 CLKL CNTENL A4L B11 B12 B13 A0L B14 OPTL I/O17L B15 B16 VSS B17 I/O20R C1 VSS C2 I/O18R C3 TDI C4 BA5L C5 BA1L C6 A9L C7 BE2L C8 CE0L C9 VSS C10 ADSL C11 A5L C12 A1L C13 VSS C14 VDDQR I/O16L I/O15R C15 C16 C17 VDDQL I/O19R VDDQR PL/FTL D1 D2 D3 D4 NC D5 BA2L D6 A10L D7 BE3L D8 CE1L D9 VSS D10 R/WL D11 A6L D12 A2L D13 VDD D14 I/O16R I/O15L D15 D16 VSS D17 I/O22L E1 VSS E2 I/O21L I/O20L BA3L E3 E4 A11L A7L BE0L VDD OEL REPEATL A3L VDD I/O17R VDDQL I/O14L I/O14R E14 E15 E16 E17 I/O23L I/O22R VDDQR I/O21R F1 F2 F3 F4 I/O12L I/O13R F14 F15 VSS F16 I/O13L F17 VDDQL I/O23R I/O24L G1 G2 G3 VSS G4 VSS G14 I/O12R I/O11L VDDQR G15 G16 G17 I/O26L H1 VSS H2 I/O25L I/O24R H3 H4 I/O9L VDDQL I/O10L I/O11R VDD J1 I/O26R VDDQR I/O25R J2 J3 J4 70V7519BF BF-208(5) 208-Pin fpBGA Top View(6) H14 H15 H16 H17 VDD J14 IO9R J15 VSS J16 I/O10R J17 VDDQL K1 VDD K2 VSS K3 VSS K4 VSS K14 VDD K15 VSS K16 VDDQR K17 I/O28R L1 VSS L2 I/O27R L3 VSS L4 I/O7R VDDQL I/O8R L14 L15 L16 VSS L17 I/O29R I/O28L VDDQR I/O27L M1 M2 M3 M4 I/O6R M14 I/O7L M15 VSS M16 I/O8L M17 VDDQL I/O29L I/O30R N1 N2 N3 VSS .


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