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KM416C254D, KM416V254D
CMOS DRAM
256K x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 262,144 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row. Power supply voltage(+5.0V or +3.3V), Access time (-5,-6 or -7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RASonly refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 EDO Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
• Extended Data Out Mode operation
FEATURES
• Part Identification - KM416C254D/DL (5V, 512 Ref.) - KM416V254D/DL (3.3V, 512 Ref.)
• 2 CAS Byte/Wrod Read/Write operation • CAS-before-RAS refresh capability • RAS-only and Hidden refresh capability • Self-refresh capability (L-ver only) • TTL(5V)/LVTTL(3.3V) compatible inputs and outputs • Early Write or output enable controlled write • JEDEC Standard pinout • Available in 40-pin SOJ 400mil and 44(40)-pin packages • Triple +5V±10% power supply (5V product) • Triple +3.3V±0.3V power supply (3.3V product)
• Active Power Dissipation Speed -5 -6 -7 • Refresh Cycles Part NO. C254D V254D VCC 5V 3.3V Refresh cycle 512 3.3V(512 Ref.) 255 235
Unit : mW 5V(512 Ref.) 605 495 440
FUNCTIONAL BLOCK DIAGRAM
Refresh period Normal 8ms L-ver 128ms
RAS UCAS LCAS W Control Clocks VBB Generator Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer
Refresh Timer
Row Decoder
• Performance Range
Refresh Control
DQ0 to DQ7
Speed -5 -6 -7
tRAC
50ns 60ns 70ns
tCAC
15ns 15ns 20ns
tRC
84ns 104ns 124ns
tHPC
20ns 25ns 30ns
Remark 5V only 5V/3.3V 5V/3.3V
A0~A8 Col. Address Buffer Refresh Counter Row Address Buffer
Memory Array 262,144 x16 Cells
OE
Column Decoder
DQ8 to DQ15
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM416C254D, KM416V254D
CMOS DRAM
PIN CONFIGURATION (Top Views)
•KM416C/V254DJ
•KM416C/V254DT
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS
VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS
(SOJ)
(TSOP-II)
Pin Name A0 - A8 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C
Pin Function Address Inputs Data In/Ou.