Document
KC73129UBA
1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
INTRODUCTION
The KC73129UBA is an interline transfer CCD area image sensor developed for CCIR 1/3 inch optical format video cameras, surveillance cameras, object detectors and image pattern recognizers. High sensitivity is achieved through the onchip micro lenses and HAD (Hole Accumulated Diode) photosensors. This chip features a field integration read out system and an electronic shutter with variable charge storage time.
16Pin Cer DIP
FEATURES
• • • • • • • • High Sensitivity Optical Size 1/3 inch Format Variable Speed Electronic Shutter (1/60, 1/100 ~ 1/10, 000sec) Low Dark Current Horizontal Register 5V Drive 16pin Ceramic DIP Package Field Integration Read Out System No DC Bias on Reset Gate
ORDERING INFORMATION
Device KC73129UBA Package 16Pin Cer DIP Operating -10 °C ~ +60 °C
STRUCTURE
• • • • • Number of Total Pixels: Number of Effective Pixels: Chip Size: Unit Pixel Size: Optical Blacks & Dummies: 537(H) × 597(V) 500(H) × 582(V) 6.00mm(H) × 4.95mm(V) 9.80µm(H) × 6.30µm(V) Refer to Figure Below Vertical 1 Line (Even Field Only)
16 7
500
30 1 Dummy Pixels Optical Black Pixels
Effective Imaging Area
OUTPUT
V-CCD
582 14
Effective Pixels
H-CCD
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1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
KC73129UBA
BLOCK DIAGRAM
(Top View)
8 VOUT
7 VSS
6 VGG
5 GND
ΦV1
4
ΦV2
3
ΦV3
2
ΦV4
1
Vertical Shift Register CCD
Vertical Shift Register CCD
Vertical Shift Register CCD
Horizontal Shift Register CCD
Vertical Shift Register CCD
9 VDD
10 GND
11 SUB
12 VL
ΦRS
13
14 NC
ΦH1
15
ΦH2
16
Figure 1. Block Diagram
PIN DESCRIPTION
Table 1. Pin Description Pin 1 2 3 4 5 6 7 8 Symbol ΦV4 ΦV3 ΦV2 ΦV1 GND VGG VSS VOUT Description Vertical CCD transfer clock 4 Vertical CCD transfer clock 3 Vertical CCD transfer clock 2 Vertical CCD transfer clock 1 Ground Output stage gate bias Output stage source bias Signal output Pin 9 10 11 12 13 14 15 16 Symbol VDD GND SUB VL ΦRS NC ΦH1 ΦH2 Description Output stage drain bias Ground Substrate bias Protection circuit bias Charge reset clock No connection Horizontal CCD transfer clock 1 Horizontal CCD transfer clock 2
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KC73129UBA
1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
ABSOLUTE MAXIMUM RATINGS (NOTE)
Table 2. Absolute Maximum Ratings Characteristics Substrate voltage Supply voltage SUB - GND VDD, VOUT, VSS - GND VDD, VOUT, VSS - SUB Vertical clock input voltage ΦV1,ΦV2, ΦV3, ΦV4 - GND ΦV1, ΦV2, ΦV3, ΦV4 - V L ΦV1, ΦV2, ΦV3, ΦV4 - SUB Horizontal clock input voltage ΦH1, ΦH2 - GND ΦH1, ΦH2 - SUB Voltage difference between vertical and horizontal clock input pins ΦV1, ΦV2, ΦV3, ΦV4 Symbols Min. -0.3 -0.3 -55 -10 -0.3 -55 -0.3 -55 Max. 55 18 10 20 30 10 10 17 15 27 ΦH1, ΦH2 ΦH1, ΦH2 - ΦV4 Output clock input voltage ΦRS, VGG - GND ΦRS, VGG - SUB Protection circuit bias voltage Operating temperature Storage temperature VL - SUB TOP TSTG -17 -0.3 -55 -55 -10 -30 17 17 15 10 10 60 80 Unit V V V V V V V V V V V V V V V °C °C
NOTE: The device can be destroyed, if the applied voltage or temperature is higher than the absolute maximum rating voltage or temperature.
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1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
KC73129UBA
DC CHARACTERISTICS
Table 3. DC Characteristics Item Output stage drain bias Output stage gate voltage Output stage source voltage Substrate voltage adjustment range Fluctuation voltage range after substrate voltage adjusted Protection circuit bias voltage Output stage drain current Symbol VDD VGG VSS VSUB ∆VSUB VL IDD Min. 14.55 1.75 Typ. 15.0 2.0 Max. 15.45 2.25 Unit V V V V % ±5% Remark
Ground through 680Ω 7.0 -3 14.5 3
The lowest vertical clock level 2.5 mA
CLOCK VOLTAGE CONDITIONS
Table 4. Clock Voltage Conditions Item Read-out clock voltage Vertical transfer clock voltage Symbol VVH1, VVH3 VVM1 ~ V VM4 VVL1 ~ V VL4 Horizontal transfer clock voltage VHH1, VHH2 VHL1, VHL2 Charge reset clock voltage VRSH VRSL Substrate clock voltage VΦSUB Min. 14.55 -0.2 -9.5 4.75 -0.2 4.75 -0.2 20 Typ. 15.0 0.0 -9.0 5.0 0.0 5.0 0.0 23.0 Max. 15.45 0.2 -8.5 5.25 0.2 5.25 0.2 25 Unit V V V V V V V V Remark High level Middle Low High Low High Low Shutter
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KC73129UBA
1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
DRIVE CLOCK WAVEFORM CONDITIONS
Read Out Clock Waveform
100% 90%
VVH 1, VVH3
10% 0% tr twh tf 0V
Vertical Transfer Clock Waveform
¥Õ V 1
VVH1
V VH VVHH VVHL
¥Õ V 3
VVHH V V HL V VH L VVHL V VH3 V VHH
V VH H
V VH
V VL H V VL 1 V VL L V VL 3 V VL L V VL H V VL
V VL
¥Õ V 2
V VH H
V VHH
V VH V VHL
¥Õ V 4
V VH V VH H
V V HH
V VH2
V VHL
V VHL
V VH 4
V VHL
V VL 2
V VL H
V VL H
V VL L V VL V VH = ( V V H 1 + V V H 2)/ 2
V VL 4
V VL L V VL
V VH H
= V V H + 0. 3V
V V L = (V V L 3 + V V L 4)/ 2 V ¥Õ V = V V H n - V V L n
(n =1~4)
V V H L = V V H - 0. 3 V V V L H = V V L + 0. 3V V V L L = V V L - 0. 3 V
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1/3 INCH CCD IMAGE SENSOR FOR CCIR CAMERA
KC73129UBA
Horizontal Transfer Clock Waveform Diagram
tr twh tf
90% V¥ÕH 10% VH L twl
Reset Gate Clock Waveform Diagram.