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Programming Specification. 12C672 Datasheet |
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PIC12C67X AND PIC12CE67X
EPROM Memory Programming Specification
This document includes the programming
specifications for the following devices:
• PIC12C671
• PIC12C672
• PIC12CE673
• PIC12CE674
1.0 PROGRAMMING THE
PIC12C67X AND PIC12CE67X
The PIC12C67X and PIC12CE67X can be pro-
grammed using a serial method. In serial mode the
PIC12C67X and PIC12CE67X can be programmed
while in the users system. This allows for increased
design flexibility.
1.1 Hardware Requirements
The PIC12C67X and PIC12CE67X requires two pro-
grammable power supplies, one for VDD (2.0V to 6.0V
recommended) and one for VPP (12V to 14V). Both
supplies should have a minimum resolution of 0.25V.
1.2 Programming Mode
The programming mode for the PIC12C67X and
PIC12CE67X allows programming of user program
memory, special locations used for ID, and the configu-
ration word for the PIC12C67X and PIC12CE67X.
Pin Diagram:
PDIP
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
1
2
3
4
8 VSS
7 GP0/AN0
6 GP1/AN1/VREF
5 GP2/T0CKI/
AN2/INT
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12C671/672 and PIC12CE673/674
Pin Name
Pin Name
GP1
CLOCK
GP0
DATA
GP3/MCLR/VPP
VPP
VDD
VDD
VSS
VSS
Legend: I = Input, O = Output, P = Power
During Programming
Pin Type
Pin Description
I Clock input
I/O Data input/output
P Programming Power
P Power Supply
P Ground
© 1998 Microchip Technology Inc.
DS40175A-page 1
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PIC12C67X and PIC12CE67X
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC12C67X family.
TABLE 2-1:
IMPLEMENTATION OF
PROGRAM MEMORY IN THE
PIC12C67X
Device
PIC12C671/
PIC12CE673
PIC12C672/
PIC12CE674
Program Memory Size
0x000 - 0x3FF (1K)
0x000 - 0x7FF (2K)
When the PC reaches the last location of the imple-
mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to
0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and
wrap around to 0x2000 (not to 0x0000). Once in con-
figuration memory, the highest bit of the PC stays a '1',
thus always pointing to the configuration memory. The
only way to point to user program memory is to reset
the part and reenter program/verify mode, as described
in Section 2.2.
The last location of the program memory space holds
the factory programmed oscillator calibration value.
This location should not be programmed except when
blank (a non-blank value should not cause the device
to fail a blank check). If blank, the programmer should
program it to a RETLW XX statement where "XX" is the
calibration value.
In the configuration memory space, 0x2000-0x20FF
are utilized. When in configuration memory, as in the
user memory, the 0x2000-0x2XFF segment is repeat-
edly accessed as the PC exceeds 0x2XFF (see
Figure 2-1).
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
0x2003].
Note 1: All other locations in PIC configuration
memory are reserved and should not be
programmed.
Note 2: Due to the secure nature of the on-board
EEPROM memory in the
PIC12CE673/674, it can be accessed only
by the user program.
DS40175A-page 2
© 1998 Microchip Technology Inc.
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EPROM Memory Programming Specification
FIGURE 2-1: PROGRAM MEMORY MAPPING
2000
ID Location
2001
ID Location
2002
ID Location
2003
ID Location
2004
Reserved
2005
Reserved
2006
Reserved
2007 Configuration Word
0
1FF
3FF
400
7FF
800
BFF
C00
FFF
1000
1KW
Implemented
Reserved
1FFF
2000
2008
2100
Reserved
Reserved
2KW
Implemented
Implemented
Reserved
Reserved
Reserved
3FFF
© 1998 Microchip Technology Inc.
DS40175A-page 3
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