Document
KT8554B/7B
1 CHIP CODECS
INTRODUCTION
The KT8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. 16-CERDIP
16-DIP300A
FEATURES
• Complete CODEC and filtering system • Meets or exceeds AT&T D3/D4 and CCITT specifications µ-Law : KT8554B, A-Law : KT8557B • On-chip auto zero, sample and hold, and precision voltage references • Low power dissipation : 60mW (operating) 3mW (standby) • ± 5V operation • TTL or CMOS compatible • Automatic power down
16-SOP-BD300 -SG
ORDERING INFORMATION
Device KT8554BJ KT8557BJ KT8557BN KT8554BN Package 16-CERDIP 16-DIP-300A 16-SOP-BD300 -SG Operating Temperature - 25 ~ 125°C - 25 ~ 70°C - 25 ~ 70°C
PIN CONFIGURATION
KT8554BD KT8557BD
V BB GNDA
1
16
VF X I + VF X I GS X TS X FS X S DX BCLK
2
15
VF RO V CC FS R DR BCLK
R/CLKSEL
3
14
4
KT8554B/7B
13
5
12
6
11
7
10
X
MCLK R/PDN
8
9
MCLK
X
Fig. 1
KT8554B/7B
1 CHIP CODECS
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 Symbol VBB GNDA VFRO VCC FSR DR BCLKR / CLKSEL MCLKR / PDN MCLKX BCLKX DX FSX TSX GSX VFXI VFXI
+
Description VBB = - 5V ±5%. Analog ground. Analog output of the receive power Amp. VCC = +5V ± 5%. Receive frame sync pulse. 8KHz pulse train. PCM data input. Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, very from 64KHz to 2.048MHz. When MCLKR is connected continuously high, the device is powered down. Normally connected continusously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. Must be1.536MHz/1.544MHz or 2.048MHz. May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. PCM data output. TX frame sync pulse. 8KHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal.
7
8 9 10 11 12 13 14 15 16
ABSOLUTE MAXIMUM RATINGS (Ta = 25oC)
Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at Any Analog Input or Output Voltage at Any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs)
Symbol VCC VBB VI (A) Vl (D) Ta T STG T LEAD
Value 7 -7 VCC + 0.3 to VBB - 0.3 VCC + 0.3 to GNDA - 0.3 - 25 to + 125 - 65 to + 150 300
Unit V V V V
o o o
C
C C
KT8554B/7B
1 CHIP CODECS
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted, VCC = 5.0V ±5%, VBB = - 5.0V ±5%, GNDA = 0V, Ta = 0 oC to 70 oC ; typical characteristics specified at VCC = 5.0V, VBB = - 5.0V, Ta = 25 oC ; all signals referenced to GNDA). Characteristic Power Dissipation ICC (DOWN) IBB (DOWN) ICC (A) IBB (A) VIL VIH IIL IIH VOL GNDA ≤ VIN≤VIL, all digital inputs VIH ≤ VIN ≤ VCC DX,IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA,open drain DX, IH = -3.2mA SIGR, IH = -1.0 mA DX, GNDA ≤ VO ≤ VCC 2.4 2.4 -10 10 2.2 -10 -10 10 10 0.4 0.4 0.4 No Load No Load No Load No Load 0.5 0.05 6.0 6.0 1.5 0.3 9.0 9.0 0.6 mA mA mA mA V V µA µA V V V V V µA Symbol Test Conditions Min Typ Max Unit
Power-Down Current Power-Down Current Active Current Active Current Digital Interface Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage
Output High Voltage Output Current in High Impedance State (TRI-STATE) Analog Interface with Receive Filter Output Resistance Load Resistance Load Capacitance Output DC Offset Voltage Input Leakage Current Input Resistance Output Resistance Load Resistance Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth Offset Voltage Common-Mode Voltage Common-Mode Rejection Ratio Power Supply Rejection Ratio
VOH IO (HZ)
RO RL CL VOO (RX) ILKG RI RO RL CL VOD (TX) GV BW VIO (TX) VCM (TX) CMRR PSRR
Pin VFRO VFRO = ±2.5V 600
1
3 500
Ω Ω pF mV nA MΩ Ω KΩ pF V V/V
-200 -2.5V≤V≤+2.5V, VFXI + or VFXI -2.5V≤V≤+2.5V, VFXI + or VFXI Closed loop, unity gain GSX GSX GSX, RL≤10KW VFXI + to GSX ±2.8 5,000 1 -20 CMRRXA > 60dB DC Test DC Test -2.5 60 60 2 10 -200 10 1
200 200 3 50
Analog Interface with Transmit input Amplifier
MHz 20 2.5 mV V dB dB
KT8554B/7B
1 CHIP CODECS
TIMING CHARACTERISTICS
(Unless.