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ISP1161 Dataheets PDF



Part Number ISP1161
Manufacturers NXP
Logo NXP
Description Full-speed Universal Serial Bus single-chip host and device controller
Datasheet ISP1161 DatasheetISP1161 Datasheet (PDF)

ISP1161 Full-speed Universal Serial Bus single-chip host and device controller Rev. 01 — 3 July 2001 Product data 1. General description The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC) which complies with Universal Serial Bus Specification Rev 1.1. These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request outp.

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ISP1161 Full-speed Universal Serial Bus single-chip host and device controller Rev. 01 — 3 July 2001 Product data 1. General description The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC) which complies with Universal Serial Bus Specification Rev 1.1. These two USB controllers, the HC and the DC, share the same microprocessor bus interface. They have the same data bus, but different I/O locations. They also have separate interrupt request output pins, separate DMA channels that include separate DMA request output pins and DMA acknowledge input pins. This makes it possible for a microprocessor to control both the USB HC and the USB DC at the same time. ISP1161 provides two downstream ports for the USB HC and one upstream port for the USB DC. Each downstream port has its own overcurrent (OC) detection input pin and power supply switching control output pin. The upstream port has its own VBUS detection input pin. ISP1161 also provides separate wakeup input pins and suspended status output pins for the USB HC and the USB DC, respectively. This makes power management flexible. The downstream ports for the HC can be connected with any USB compliant USB devices and USB hubs that have USB upstream ports. The upstream port for the DC can be connected to any USB compliant USB host and USB hubs that have USB downstream ports. c c The DC is compliant with most device class specifications such as Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices and Human Interface Devices. ISP1161 is well suited for embedded systems and portable devices that require a USB host only, a USB device only, or a combined and configurable USB host and USB device capabilities. ISP1161 brings high flexibility to the systems that have it built-in. For example, a system that has ISP1161 built-in allows it not only to be connected to a PC or USB hub that has a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard, USB mouse, among others. ISP1161 enables peer-to-peer connectivity between embedded systems. An interesting application example is to connect a ISP1161 HC with a ISP1161 DC. Let us see an example of ISP1161 being used in a Digital Still Camera (DSC) design. Figure 1 shows ISP1161 being used as a USB DC. Figure 2 shows ISP1161 being used as a USB HC. Figure 3 shows ISP1161 being used as a USB HC and a USB DC at the same time. Philips Semiconductors ISP1161 Full-speed USB single-chip host and device controller EMBEDDED SYSTEM µP µP SYSTEM MEMORY PC (host) µP bus I/F ISP1161 HOST/ DEVICE USB cable USB I/F USB I/F USB device DSC MGT926 Fig 1. ISP1161 operating as a USB device. EMBEDDED SYSTEM µP µP SYSTEM MEMORY µP bus I/F ISP1161 HOST/ DEVICE USB cable USB I/F PRINTER (device) USB I/F DSC USB host MGT927 Fig 2. ISP1161 operating as a stand-alone USB host. 9397 750 08313 © Philips Electronics N.V. 2001. All rights reserved. Product data Rev. 01 — 3 July 2001 2 of 130 Philips Semiconductors ISP1161 Full-speed USB single-chip host and device controller EMBEDDED SYSTEM µP µP SYSTEM MEMORY PC (host) µP bus I/F DSC PRINTER (device) ISP1161 HOST/ DEVICE USB cable USB I/F USB device USB host MGT928 USB cable USB I/F USB I/F USB I/F Fig 3. ISP1161 operating as both USB host and device simultaneously. 2. Features s s s s s s Complies with Universal Serial Bus Specification Rev 1.1 Combines HC and DC in a single chip On-chip DC complies with most Device Class specifications Both HC and DC can be accessed by an external microprocessor via separate I/O port addresses Selectable one or two downstream ports for HC and one upstream port for DC High speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors (Hitachi SH-3 and SH-4, MIPS-based RISC, ARM7/9, StrongARM, etc.). Maximum 15 Mbyte/s data transfer rate between microprocessor and the HC, 11.1 Mbyte/s data transfer rate between microprocessor and the DC Supports single-cycle burst mode and multiple-cycle burst mode DMA operations Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC Built in separate FIFO buffer RAM for HC (4 kbytes) and DC (2462 bytes) Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions 6 MHz crystal oscillator with integrated PLL for low EMI Controllable LazyClock (24 kHz) output during ‘suspend’ Clock output with programmable frequency (3 to 48 MHz) Software controlled connection to the USB bus (SoftConnect) on upstream port for the DC Good USB connection indicator that blinks with traffic (GoodLink) for the DC Built-in software selectable internal 15 kΩ pull-down resistors for HC downstream ports Dedicated pins for suspend sensing output and wakeup control input for flexible applications Global hardware reset.


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