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ispGDX120A-5T176 Dataheets PDF



Part Number ispGDX120A-5T176
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable Generic Digital CrosspointTM
Datasheet ispGDX120A-5T176 DatasheetispGDX120A-5T176 Datasheet (PDF)

ispGDX Family TM In-System Programmable Generic Digital Crosspoint Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving TQFP, PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundar.

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ispGDX Family TM In-System Programmable Generic Digital Crosspoint Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving TQFP, PQFP and BGA Packaging — Dedicated IEEE 1149.1-Compliant Boundary Scan Test — PCI Compliant Output Drive • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 5V Power Supply — 5.0ns Input-to-Output/5.0ns Clock-to-Output Delay — Low-Power: 40mA Quiescent Icc — Balanced 24mA Output Buffers with Programmable Slew Rate Control — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology — 100% Tested • ispGDX OFFERS THE FOLLOWING ADVANTAGES — In-System Programmable — Lattice ISP or JTAG Programming Interface — Only 5V Power Supply Required — Change Interconnects in Seconds — Reprogram Soldered Devices • FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs — Individual I/O Tri-state Control with Polarity Control — Dedicated Clock Input Pins (two or four) or Programmable Clocks from I/O Pins (from 20 up to 40) — Up to 4:1 Dynamic Path Selection — Programmable Output Pull-up Resistors — Outputs Tri-state During Power-up (“Live Insertion” Friendly) • DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE — MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level Simulation TM Functional Block Diagram I/O Pins D ISP Control I/O Pins C I/O Pins A I/O Cells Global Routing Pool (GRP) I/O Cells Boundary Scan Control I/O Pins B Description The ispGDX architecture provides a family of fast, flexible programmable devices to address a variety of systemlevel digital signal routing and interface requirements including: • Multi-Port Multiprocessor Interfaces • Wide Data and Address Bus Multiplexing (e.g. 4:1 High-Speed Bus MUX) • Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc) • Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The ispGDX Family consists of three members with 80, 120 and 160 Programmable I/Os. These devices are available in packages ranging from the 100-pin TQFP to the 208-pin PQFP. The devices feature fast operation, with input-to-output signal delays (Tpd) of 5ns and clockto-output delays of 5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Rout- Copyright © 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2000 ispgdx_08 1 Specifications ispGDX Family Description (Continued) ing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK) and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. OE, CLK and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clock-to-output delays. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDX devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and source current and can be tied together in parallel for greater drive. Programmable output slew rate can be defined independently f.


ispGDX120A-5Q160 ispGDX120A-5T176 ispGDX120A-7Q160


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