DatasheetsPDF.com

ISPL1048E-90LQ Dataheets PDF



Part Number ISPL1048E-90LQ
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description High-Density Programmable Logic
Datasheet ISPL1048E-90LQ DatasheetISPL1048E-90LQ Datasheet (PDF)

ispLSI 1048E ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Functionally and Pin-out Compatible to ispLSI 1048C TECHNOLOGY • HIGH PERFORMANCE — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inp.

  ISPL1048E-90LQ   ISPL1048E-90LQ


Document
ispLSI 1048E ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — Functionally and Pin-out Compatible to ispLSI 1048C TECHNOLOGY • HIGH PERFORMANCE — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Eraseable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispLSI DEVELOPMENT TOOLS ispVHDL™ Systems — VHDL/Verilog-HDL/Schematic Design Options — Functional/Timing/VHDL Simulation Options ispDS+™ VHDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation — Static Timing Analyzer ispDS™ Software — Lattice HDL or Boolean Logic Entry — Functional Simulator and Waveform Viewer ISP Daisy Chain Download Software E2CMOS® Functional Block Diagram Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0 Output Routing Pool Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5 Output Routing Pool 0139G1A-isp D Q A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool D6 Logic D Q Global Routing Pool (GRP) Array D Q GLB D4 D3 D2 D1 D0 D Q C0 C1 C2 C3 C4 C5 C6 C7 Output Routing Pool CLK Description The ispLSI 1048E is a High-Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 1048E offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global output enable pins and two additional dedicated inputs. The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device. Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com July 1998 1048E_08 1 Specifications ispLSI 1048E Functional Block Diagram Figure 1. ispLSI 1048E Functional Block Diagram I/O I/O I/O I/O 95 94 93 92 RESET GOE 0 GOE 1 I/O I/O I/O I/O 91 90 89 88 I/O I/O I/O I/O 87 86 85 84 I/O I/O I/O I/O 83 82 81 80 IN IN 11 10 I/O I/O I/O I/O 79 78 77 76 I/O I/O I/O I/O 75 74 73 72 I/O I/O I/O I/O 71 70 69 68 I/O I/O I/O I/O 67 66 65 64 IN 9 IN 8 Input Bus Generic Logic Blocks (GLBs) F7 F6 Output Routing Pool (ORP) F5 F4 F3 F2 F1 F0 E7 E6 Input Bus Output Routing Pool (ORP) E5 E4 E3 E2 E1 E0 IN 7 IN 6 I/O 63 I/O 62 I/O 61 I/O 60 D7 I/O 0 I/O 1 I/O 2 I/O 3 A0 A1 Output Routing Pool (ORP) D6 Output Routing Pool (ORP) D5 I/O 59 I/O 58 I/O 57 D4 D3 D2 D1 D0 lnput Bus Input Bus I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Global Routing Pool (GRP) I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 C0 C1 C2 C3 C4 C5 C6 C7 Clock Distribution Network Output Routing Pool (ORP) Megablock Input Bus ispEN/NC IN 2 SDO/ IN 3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 IN SCLK/ I/O I/O I/O I/O 4 IN 5 32 33 34 35 Output .


ISPL1048E-70LTI ISPL1048E-90LQ ISPL1048E-90LQI


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)