IW4013B

TECHNICAL DATA IW4013B Dual D Flip-Flop High-Voltage Silicon-Gate CMOS The IW4013B consists of two identical, independent data-type flipflops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices can be used for shift register applications, and, by connecting Q output to the data input, for counter and toggle applications. The logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line, respectively. Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4013BN Plastic IW4013BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Clock Data Reset Set L H X X PIN 14 =VCC PIN 7 = GND X X X X X L L L H L H L L L L H H Outputs Q L H Q L H H Q H L Q H L H X = don’t care 19 IW4013B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor S...