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IMIC9531 Dataheets PDF



Part Number IMIC9531
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description PCIX I/O System Clock Generator
Datasheet IMIC9531 DatasheetIMIC9531 Datasheet (PDF)

C9531 PCIX I/O System Clock Generator with EMI Control Features Features • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter • Input clock frequency of 25 MHz to 33 MHz • Output frequencies of XINx1, XINx2, XINx3 and XINx4 • One output bank of 5 clocks. • One REF XIN clock output. • SMBus clock control interface for individual clock disabling and SSCG control • Output clock duty cycle is 50% (± 5%) • < 250 ps skew between output clocks within a bank • Output jitter <175 p.

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C9531 PCIX I/O System Clock Generator with EMI Control Features Features • Dedicated clock buffer power pins for reduced noise, crosstalk and jitter • Input clock frequency of 25 MHz to 33 MHz • Output frequencies of XINx1, XINx2, XINx3 and XINx4 • One output bank of 5 clocks. • One REF XIN clock output. • SMBus clock control interface for individual clock disabling and SSCG control • Output clock duty cycle is 50% (± 5%) • < 250 ps skew between output clocks within a bank • Output jitter <175 ps • Spread Spectrum feature for reduced electromagnetic interference (EMI) • OE pin for entire output bank enable control and testability • 28-pin SSOP and TSSOP packages Table 1. Test Mode Logic Table[1] Input Pins OE HIGH HIGH HIGH HIGH LOW S1 LOW LOW HIGH HIGH X S0 LOW HIGH LOW HIGH X Output Pins CLK XIN 2 * XIN 3 * XIN 4 * XIN REF XIN XIN XIN XIN Three-state Three-state Block Diagram Pin Configuration REF 1 2 3 4 5 6 28 27 26 25 24 23 SDATA SCLK VSS VDDP CLK0 CLK1 CLK2 VSS VDDP CLK3 CLK4 VDDA VSS SSCG# SSCG# SSCG Logic /N 1 0 CLK0 CLK1 CLK2 CLK3 CLK4 OE GOOD# REF VDD XIN XOUT VSS S0 S1 GOOD# VSS IA0 IA1 IA2 VDDA OE C9531 XIN XOUT 7 8 9 10 11 12 13 14 22 21 20 19 18 17 16 15 SDATA SCLK IA(0:2) S(0,1) I 2C Control Logic Note: 1. XIN is the frequency of the clock on the device’s XIN pin. Cypress Semiconductor Corporation Document #: 38-07034 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 12, 2003 C9531 Pin Description[3] Pin[2] 3 4 1 14* 24, 23, 22, 19, 18 8 XIN XOUT REF OE CLK(0:4) GOOD# Name PWR[4] VDDA VDDA VDD VDD VDDP VDD I/O I O O I O O Description Crystal Buffer Input Pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. Crystal Buffer Output Pin. Connects to a crystal only. When a Can Oscillator is used or in test mode, this pin is kept unconnected. Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz. Output Enable for Clock Bank. Causes the CLK (0:4) output clocks to be in a three-state condition when driven to a logic low level. A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. When his output signal is a logic low level, it indicates that the output clocks of the bank are locked to the input reference clock. This output is latched. Clock Bank Selection Bits. These control the clock frequency that will be present on the outputs of the bank of buffers. See table on page one for frequency codes and selection values. 3.3V common power supply pin for all PCI clocks CLK (0:4). SMBus Address Selection Input Pins. See Table 3 on page 3. Spread Spectrum Clock Generator. Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. Data for the Internal SMBus Circuitry. See Table 3 on page 3. Clock for the Internal SMBus Circuitry. See Table 3 on page 3. Power for Internal Analog Circuitry. This supply should have a separately decoupled current source from VDD. Powe.


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