Clock Recovery. 1417G5A Datasheet

1417G5A Recovery. Datasheet pdf. Equivalent

1417G5A Datasheet
Recommendation 1417G5A Datasheet
Part 1417G5A
Description NetLight 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Recovery
Feature 1417G5A; Data Sheet January 2000 NetLight ® 1417G5 and 1417H5-Type ATM/SONET/SDH Transceivers with Clock Rec.
Manufacture Agere Systems
Datasheet
Download 1417G5A Datasheet




Agere Systems 1417G5A
Data Sheet
January 2000
NetLight ® 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Available in a small form factor, RJ-45 size, plastic package,
the 1417G5 and 1417H5-Type are high-performance, cost-
effective transceivers for ATM/SONET/SDH applications at
155 Mbits/s and 622 Mbits/s.
Features
s SONET/SDH Compliant (ITU-T G.957 Specifica-
tions)
— IR-1/S1.1, S4.1
s Small form factor, RJ-45 size, multisourced 20-pin
package
s Requires single 3.3 V power supply
s Clock recovery
s LC duplex receptacle
s Analog alarm outputs
s Uncooled 1300 nm laser transmitter with automatic
output power control
s Transmitter disable input
s Wide dynamic range receiver with InGaAs PIN
photodetector
s LVTTL signal-detect output
s Low power dissipation
s Raised ECL (PECL) logic data and clock interfaces
s Operating case temperature range: –40 °C to
+85 °C
s Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability
Description
The 1417G5 and 1417H5 transceivers are high-
speed, cost-effective optical transceivers that are
compliant with the International Telecommunication
Union Telecommunication (ITU-T) G.957 specifica-
tions for use in ATM, SONET, and SDH applications.
The 1417G5 operates at the OC-3/STM-1 rate of
155 Mbits/s, and the 1417H5 operates at the OC-12/
STM-4 rate of 622 Mbits/s. The transceiver features
Agere Systems high-reliability optics and is pack-
aged in a narrow-width plastic housing with an LC
duplex receptacle. This receptacle fits into an RJ-45
form factor outline. The 20-pin package and pinout
conform to a multisource transceiver agreement.
The transmitter features differential PECL logic level
data inputs and a LVTTL logic level disable input. The
receiver features differential PECL logic level data
and clock outputs and a LVTTL logic level signal-
detect output.



Agere Systems 1417G5A
NetLight 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Data Sheet
January 2000
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Supply Voltage
Operating Case Temperature Range
Storage Case Temperature Range
Lead Soldering Temperature/Time
Operating Wavelength Range
Symbol
Min
Max
Unit
VCC 0 3.6 V
TC –40 85 °C
Tstg –40 85 °C
250/10
°C/s
λ 1.1 1.6 nm
Pin Information
TX
20 19 18 17 16 15 14 13 12 11
20-PIN MODULE - TOP VIEW
1 2 3 4 5 6 7 8 9 10
RX
Figure 1. 1417G5 and 1714H5 Transceivers, 20-Pin Configuration, Top View
1-967(F).b
Table 1. Transceiver Pin Descriptions
Pin
Number
MS
1
2
3
4
5
6
7
8
9
10
Symbol
Name/Description
MS
Photode-
tector Bias
VEER
VEER
CLK–
CLK+
VEER
VCCR
SD
RD–
RD+
Receiver
Mounting Studs. The mounting studs are provided for transceiver mechani-
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
Photodetector Bias. This lead supplies bias for the PIN photodetector diode.
Receiver Signal Ground.
Receiver Signal Ground.
Received Recovered Clock Out. The rising edge occurs at the rising edge of
the received data output. The falling edge occurs in the middle of the received
data bit period.
Received Recovered Clock Out. The falling edge occurs at the rising edge
of the received data output. The rising edge occurs in the middle of the
received data bit period.
Receiver Signal Ground.
Receiver Power Supply.
Signal Detect.
Normal operation: logic one output.
Fault condition: logic zero output.
Received DATA Out. No internal terminations will be provided.
Received DATA Out. No internal terminations will be provided.
Logic
Family
NA
NA
NA
NA
PECL
PECL
NA
NA
LVTTL
PECL
PECL
2 Agere Systems Inc.



Agere Systems 1417G5A
Data Sheet
January 2000
NetLight 1417G5 and 1417H5-Type
ATM/SONET/SDH Transceivers with Clock Recovery
Pin Information (continued)
Table 1. Transceiver Pin Descriptions (continued)
Pin
Number
11
12
13
14
15
16
17
18
19
20
Symbol
VCCT
VEET
TDIS
TD+
TD–
VEET
BMON(–)
BMON(+)
PMON(–)
PMON(+)
Name/Description
Transmitter
Transmitter Power Supply.
Transmitter Signal Ground.
Transmitter Disable.
Transmitter Data In.
Transmitter Data In Bar.
Transmitter Signal Ground.
Laser Diode Bias Current Monitor—Negative End. The laser bias current
is accessible as a dc-voltage by measuring the voltage developed across pins
17 and 18.
Laser Diode Bias Current Monitor—Positive End. See pin 17 description.
Laser Diode Optical Power Monitor—Negative End. The back-facet diode
monitor current is accessible as a dc-voltage by measuring the voltage devel-
oped across pins 19 and 20.
Laser Diode Optical Power Monitor—Positive End. See pin 19 description.
Logic
Family
NA
NA
LVTTL
PECL
PECL
NA
NA
NA
NA
NA
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA ® stan-
dard EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD. Agere Systems employs a human-body model
(HBM) for ESD-susceptibility testing and protection-
design evaluation. ESD voltage thresholds are depen-
dent on the critical parameters used to define the
model. A standard HBM (resistance = 1.5 k, capaci-
tance = 100 pF) is widely used and, therefore, can be
used for comparison purposes. The HBM ESD thresh-
old established for the 1417G5 and 1417H5 transceiv-
ers is ±1000 V.
Application Information
The 1417 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (PECL), the device should be thought of as
an analog component. When laying out system appli-
cation boards, the 1417 transceiver should receive the
same type of consideration one would give to a sensi-
tive analog component.
Agere Systems Inc.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high-gain, wide-
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
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