|
|
Clock Recovery. 1430G5LL Datasheet |
|
|
|
Data Sheet, Rev 1.
August 2001
NetLight ® 1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Available in a small form factor, plastic package, the
1430G5 are high-performance, cost-effective transceivers for
SONET/SDH long-reach applications at 155 Mbits/s.
Features
s SONET LR-1/SDH L1.1 Compliant (ITU-T G.957
Specifications)
s Small form factor, RJ-45 size, multisourced 20-pin
package
s Requires single 3.3 V power supply
s Clock recovery
s Fiber pigtail
s Uncooled 1300 nm laser transmitter with automatic
output power control
s Transmitter disable input
s Analog alarm outputs
s Wide dynamic range receiver with InGaAs PIN
photodetector
s LVTTL signal-detect output
s Low power dissipation
s Raised ECL (LVPECL) logic data interfaces
s Operating case temperature range: –40 °C to
+85 °C
s Agere Systems Inc. Reliability and Qualification
Program for built-in quality and reliability
Description
The 1430G5-Type transceiver is a high-speed, cost-
effective optical transceiver that is compliant with the
International Telecommunication Union Telecommu-
nication (ITU-T) G.957 specifications for use in
SONET and SDH long-reach applications. The
1430G5 operates at the OC-3/STM-1 rate of
155 Mbits/s. The transceiver features Agere Sys-
tems’ optics and is packaged in a narrow-width plas-
tic housing with two 1 meter fiber pigtails terminated
with LC connectors. The 20-pin package and pinout
conform to a multisource transceiver agreement.
The transmitter features differential LVPECL logic
level data inputs, a LVTTL logic level disable input.
The receiver features differential LVPECL logic level
data and clock outputs, and a LVTTL logic level
signal-detect output.
|
NetLight 1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Data Sheet, Rev 1.
August 2001
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Supply Voltage
Operating Case Temperature Range
Storage Case Temperature Range
Lead Soldering Temperature/Time
Operating Wavelength Range
Symbol
Min
Max
Unit
VCC 0 3.6 V
TC –40 85 °C
Tstg –40 85 °C
—
—
250/10
°C/s
λ 1.1 1.6 nm
Pin Information
TX
20 19 18 17 16 15 14 13 12 11
20-PIN MODULE - TOP VIEW
1 2 3 4 5 6 7 8 9 10
RX
Figure 1. 1430G5 and 1430H5-Type Transceivers, 20-Pin Configuration, Top View
1-967(F).b
Table 1. Transceiver Pin Descriptions
Pin
Number
MS
1
2
3
4
5
6
7
8
9
10
Symbol
Name/Description
Logic
Family
Receiver
MS Mounting Studs. The mounting studs are provided for transceiver mechani- NA
cal attachment to the circuit board. They may also provide an optional con-
nection of the transceiver to the equipment chassis ground.
Photode- Photodetector Bias. This lead supplies bias for the PIN photodetector diode.
tector Bias
NA
VEER Receiver Signal Ground.
NA
VEER
CLK–
Receiver Signal Ground.
Received Recovered Clock Out. The rising edge occurs at the rising edge of
the received data output. The falling edge occurs in the middle of the received
data bit period.
NA
LVPECL
CLK+
Received Recovered Clock Out. The falling edge occurs at the rising edge
of the received data output. The rising edge occurs in the middle of the
received data bit period.
LVPECL
VEER
VCCR
Receiver Signal Ground.
Receiver Power Supply.
NA
NA
SD Signal Detect.
Normal operation: logic one output.
Fault condition: logic zero output.
LVTTL
RD– Received DATA Out. No Internal terminations will be provided.
LVPECL
RD+ Received DATA Out. No internal terminations will be provided.
LVPECL
2 Agere Systems Inc.
|
Data Sheet, Rev 1.
August 2001
NetLight 1430G5 Type SONET/SDH
Long-Reach Transceivers with Clock Recovery
Pin Information (continued)
Table 1. Transceiver Pin Descriptions (continued)
Pin
Number
11
12
13
14
15
16
17
18
19
20
Symbol
VCCT
VEET
TDIS
TD+
TD–
VEET
Bmon–
BMON+
PMON–
PMON+
Name/Description
Logic
Family
Transmitter
Transmitter Power Supply.
NA
Transmitter Signal Ground.
NA
Transmitter Disable.
LVTTL
Transmitter DATA In.
LVPECL
Transmitter DATA In Bar.
Transmitter Signal Ground.
LVPECL
NA
Laser Diode Bias Current Monitor—Negative End. The laser bias current
is accessible as a dc-voltage by measuring the voltage developed across pins
17 and 18.
NA
Laser Diode Bias Current Monitor—Positive End. See pin 17 description.
NA
Laser Diode Optical Power Monitor—Negative End. The back-facet diode
monitor current is accessible as a dc-voltage by measuring the voltage devel-
oped across pins 19 and 20.
NA
Laser Diode Optical Power Monitor—Positive End. See pin 19 description. NA
Electrostatic Discharge
Caution: This device is susceptible to damage as
a result of electrostatic discharge (ESD).
Take proper precautions during both
handling and testing. Follow EIA ® Stan-
dard EIA-625.
Although protection circuitry is designed into the
device, take proper precautions to avoid exposure to
ESD.
Agere Systems employs a human-body model (HBM)
for ESD-susceptibility testing and protection-design
evaluation. ESD voltage thresholds are dependent on
the critical parameters used to define the model. A
standard HBM (resistance = 1.5 kΩ, capacitance =
100 pF) is widely used and, therefore, can be used for
comparison purposes. The HBM ESD threshold estab-
lished for the 1430G5 transceiver is ±1000 V.
Application Information
The 1430 receiver section is a highly sensitive fiber-
optic receiver. Although the data outputs are digital
logic levels (LVPECL), the device should be thought of
as an analog component. When laying out system
application boards, the 1430 transceiver should receive
the same type of consideration one would give to a
sensitive analog component.
Printed-Wiring Board Layout Considerations
A fiber-optic receiver employs a very high gain, wide
bandwidth transimpedance amplifier. This amplifier
detects and amplifies signals that are only tens of nA in
amplitude when the receiver is operating near its sensi-
tivity limit. Any unwanted signal currents that couple
into the receiver circuitry cause a decrease in the
receiver's sensitivity and can also degrade the perfor-
mance of the receiver's signal detect (SD) circuit. To
minimize the coupling of unwanted noise into the
receiver, careful attention must be given to the printed-
wiring board.
At a minimum, a double-sided printed-wiring board
(PWB) with a large component-side ground plane
beneath the transceiver must be used. In applications
that include many other high-speed devices, a multi-
layer PWB is highly recommended. This permits the
placement of power and ground on separate layers,
which allows them to be isolated from the signal lines.
Multilayer construction also permits the routing of sen-
sitive signal traces away from high-level, high-speed
signal lines. To minimize the possibility of coupling
noise into the receiver section, high-level, high-speed
signals such as transmitter inputs and clock lines
should be routed as far away as possible from the
receiver pins.
Agere Systems Inc.
3
|
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |