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S3P72K8 Dataheets PDF



Part Number S3P72K8
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description singl-chip CMOS microcontroller
Datasheet S3P72K8 DatasheetS3P72K8 Datasheet (PDF)

S3C72K8/P72K8 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 27 pins of the 80-pin QFP p.

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S3C72K8/P72K8 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72K8 singl-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM48 (Samsung Arrageable Microcontrollers). With a two-channel comparator, up-to320-dot LCD direct drive capability, 8-bit timer/counter, watchdog timer and serial I/O, the S3C72K8 offers an excellent design solution for a wide variety of applications which require LCD functions. Up to 27 pins of the 80-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events. In addition, the S3C72K8's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C72K8 microcontroller is also available is OTP (one time programmable) version, S3P72K8. S3P72K8 microcontroller has an one-chop 8 Kbyte one time programmable EPROM instead of masked ROM. The S3P72K8 is comparable to S3C72K8, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72K8/P72K8 FEATURES Memory — 8 K × 8-bit RAM — 1,024 × 4-bit ROM 27 I/O Pins — Input only: 4 pins — I/O: 15 pins — Output: maximum 8 pins for 1-bit level output (sharing with segment driver outputs) Comparator — Two channel mode: internal reference (4-bit resolution) — One channel mode: external reference LCD Controller/Driver — 40 segments and 8 common terminals — 3, 4 and 8 common selectable — Internal resistor circuit for LCD bias — All dot can be switched on/off 8-Bit Basic Timer — 4 interval timer functions — Watchdog timer 8-Bit Timer/Counter — Programmable 8-bit timer — External event counter — Arbitrary clock frequency output — External clock signal divider — Serial I/O interface clock generator 8-Bit Serial I/O Interface — 8-bit transmit/receive mode — 8-bit receive only mode — LSB-first or MSB-first transmission selectable — Internal or external clock source Bit Sequential Carrier — Support 16-bit serial data transfer in arbitrary format Instruction Execution Times — 0.67 us at 6 MHz (minimum) — 0.95 µs at 4.19 MHz (minimum) — 122 µs at 32,768 kHz (minimum) Operating Temperature — – 40 °C to 85 °C Operating Voltage Range — 2.0 V to 5.5 V Package Type — 80-pin QFP Two Power-Down Modes — Idle mode (only CPU clock stops) — Stop mode (main system oscillation stops) — Subsystem clock stop mode Oscillation Sources — Crystal, ceramic, or External RC for system clock — Main system clock frequency: 0.4 MHz–6 MHz — Subsystem clock frequency: 32,768 kHz — CPU clock divider circuit (by 4, 8, or 64) Interrupts — Three internal vectored interrupts: INTB, INTT0, INTS — Four external vectored interrupts: INT0, INT1, INT4, INTK — Two quasi-interrupts: INT2, INTW Memory-Mapped I/O Structure — Data memory bank 15 Watch Timer — Timer interval generation: 0.5 s, 3.9 ms at 32,768 Hz — Four frequency outputs to BUZ pin — Clock source generation for LCD 1-2 S3C72K8/P72K8 PRODUCT OVERVIEW BLOCK DIAGRAM RESET Watchdog Timer Basic Timer Interrupt Control Block XIN XOUT XTIN XTOUT LCD Driver/ Controller Clock Stack Pointer I/O Port 2 VLC1-VLC5 COM0-COM7 SEG0-SEG31 P5.0/SEG32P5.7/SEG39 P2.0-P2.3 P3.0 P3.1 P3.2/LCDSY P3.3/CLDCK P4.0/CLO P4.1/TCL0 P4.2/TCLO0 Watch Timer SIO P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 Internal Interrupts Instruction Decoder Program Counter I/O Port 3 Program Status Word I/O Port 4 Flags 8-Bit Timer/ Counter 8 Kbyte Program Memory I/O Port 0 Arithmetic and Logic Unit Comparator P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4 Input Port 1 1024 x 4-Bit Data Memory Figure 1-1. S3C72K8 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72K8/P72K8 PIN ASSIGNMENTS SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32/P5.0 SEG33/P5.1 SEG34/P5.2 SEG35/P5.3 SEG36/P5.4 SEG37/P5.5 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P5.6/SEG38 P5.7/SEG39 VLC1 VLC2 VLC3 VLC4 VLC5 P0.0/SCK/K0 P0.1/SO/K1 P0.2/SI/K2 P0.3/BUZ/K3 VDD VSS XOUT XIN TEST XTIN XTOUT RESET P1.0/INT0/CIN0 P1.1/INT1/CIN1 P1.2/INT2 P1.3/INT4 P2.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 S3C72K8 (80-QFP-1420C) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM7 COM6 Figure 1-2. S3C72K8 80-QFP Pin Assignment 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 COM5 COM4 COM3 COM2 COM1 COM0 TCLO0/P4.2 TCL0/P4.1 CLO/P4.0 LCDCK/P3.3 LCDSY/P3.2 P3.1 P3.0 P2.3 P2.2 P2.1 1-4 S3C72K8/P72K8 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C72K8 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit or 4-bit read/write and test is possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 4-b.


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