S5C7212X

TIMING & SYNC. GENERATOR FOR B/W CCD S5C7212X01 INTRODUCTION The S5C7212X01 is a CMOS integrated circuit designed for making various timing pulses for B/W CCD camera. 48-QFP-0707 FEATURES Compatible with both EIA and CCIR mode ( EIA : S5F325NW02 / S5F325NU02 CCIR : S5F329PW02 / S5F329PU02 ) Built in auto iris function (Electronic Exposure) Mirror mode timing generation Field interlace mode only Timing and sync one chip IC Oscillation frequency EIA : 19.06992MHz, CCIR : 18.93750MHz ORDERING INFORMATION Device S5C7212X01-E0R0 Package 48-QFP-0707 Operating -20 °C − 75 °C APPLICATION B/W CCD Camera BLOCK DIAGRAM XSUB XSG1 XSG3 25 ϕH4 ϕH3 ϕH1 ϕH2 XV2 XV1 XV3 38 37 36 35 33 30 29 28 27 26 24 22 SHP SHD CL 43 X2 41 X1 40 TS2 45 GATE2 1/2 GATE1 XV4 RG 21 1/606 Horizontal ROM F/F 18 17 16 15 14 13 CLP1 CLP2 CLP3 DFDO CLEN WIN TS1 46 TS0 47 PWR 48 1/525 or 1/625 High/Low Control Shutter Speed ROM Vertical ROM Shutter Speed Count F/F Shutter Speed Control 1 MD2 2 MD1 3 EE1 4 EE2 7 FLD 8 PBLK 9 CSYNC 10 CBLK 11 VD 12 HD 1 S5C7212X01 TIMING & SYNC. GENERATOR FOR B/W CCD PIN DESCRIPTION No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol MD2 MD1 EE1 EE2 VSS1 VDD1 FLD PBLK CSYNC CBLK VD HD WIN CLEN DFDO CLP3 CLP2 CLP1 VSS2 VDD2 SHD SHP VSS3 XV4 XSG3 V3 XSG1 XV1 XV2 XSUB VDD3 VSS4 I/O I I I I O O O O O O O O O O O O O O O O O O O O O Description CCIR/EIA mode selection NORMAL/MIRRO...