Document
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
INTRODUCTION
S5T8809 is a superior low-power-programmable PLL frequency synthesizer which can be used in high performance / Simple application for a Wide Area Pager system. S5T8809 consists of 2 kinds of divider block including a 19-bit Shift register, 16/18-bit Latch, 13/15bits R-counter and 16/18-bit NCounter, 32/33 Prescaler, and a phase detector block including a Phase detector, Lock detector and a Charge pump. S5T8809 also has a battery saving mode which can control each register block by serial control data from the µ-controller (MICOM) and it also has boost up signal output for fast locking.
16-TSSOP-0044
( Magnification = 1 : 4 )
FEATURES
• • • Maximum operating frequency: 330MHz @ 300mVP-P, VDD1 = 1.0V, VDD2 = 3.0V On-chip reference oscillator supports external crystal which oscillates up to 23MHz Superior supply current: — FFIN = 310MHz, IDD1 = 0.8mA (Typ.) @ VDD1 = 1.0V, VDD2 = 3.0V Operating voltage: VDD1 = 0.95 to 1.5V and VDD2 = 2.0 to 3.3V Excellent Divider range: — Ref. Divider: FRC (0): 1 / 40 to 1 / 65528 (Multiple): Default FRC (1): 1 / 5 to 1 / 32767 — Rx Divider: PBC (0): 1 / 1056 ~ 1 / 65535: Default PBC (1): 1 / 1056 ~ 1 / 262143 • • Boost-up signal output for Fast Locking In the Standby mode, VDD1 block can be controlled by BSB Pin status — Standby current consumption: 10µA (Max.) • • • • Programmable control the output of LD to reduce internal noise Programmable 17 / 19-bit shift register value controlled by PBC Charge pump output circuitry for passive filter Package type: 16−TSSOP (0.65mm)
• •
ORDERING INFORMATION
Device +S5T8809X01-R0B0
+: New Product
Package 16−TSSOP −0044
Operating Temperature −25°C to +75°C
1
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
BLOCK DIAGRAM
OSCI 1 OSCO 2 VDD1 VDD2
Amp
1/8 Prescaler
13 or 15 Bit Divider ( R - counter ) FRC 13 / 15
Schmitt Trigger
16
Lock Detector
10
LD
VDD2
3
16 or 18Bit Latch 2 (Test1. LDC) Schmitt Trigger 16 / 18 Phase Detector Charge Pump 5
BSB EN DATA CLK
14 13 12 11 Shift Register * 17 or 19 Bit
PDO
Fast Lock
4
FL
18 VSS 6 16 or 18Bit Latch
Schmitt Trigger
15
FLC
18 Fin VDD1 7 8 VDD1 Amp 32/33 Prescaler 5 Bit Swallow Counter 11 or 13 bit Main Counter
POR
Schmitt Trigger
9
PBC
2
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
PIN CONFIGURATION
OSCI OSCO VDD2 FL PDO VSS Fin VDD1
1 2 3 4 5 6 7 8
16 15 14
TEST FLC BSB EN DATA CLK LD PBC
KS8809D S5T8809
13 12 11 10 9
3
S5T8809
PLL FREQUENCY SYNTHESIZER FOR PAGE
PIN DESCRIPTION
Pin No 1 2 3 4 5 6 7 8 9 Symbol OSCI OSCO VDD2 FL PDO VSS Fin VDD1 PBC Description These input / output pins generate the reference frequency. In case of OSCI Pin, external reference frequency can be used through the AC coupling. The highest potential supply terminal that can be supplied up to 2.0 ~ 3.3V. Booster signal output for fast locking. The output of RX phase detector terminal for passive loop filter. There are 3-kinds of output signal states according to Rx loop error. Ground terminal Input terminal for the frequency from VCO. Output frequency from VCO was inputted through AC coupling Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 ~ 1.5V from VSS. This is an input for programmable bit control which has Schmitt Trigger architecture, Internally biased pull-up. High = 16 Bits N-Divider (Default: ND0 ~ ND15) Low = 18 Bits N-Divider (ND0 ~ ND7) cf) R-divider bits will be changed by the FRC bit of program The output of phase detector can be controlled by R-counter register. When the LDC bit of R-counter set to Low, the output will be disabled to reduce a noise problem, but if it is set to High, the output will be enabled to show an lock / unlock status that is the error width between to Ref. signal and the VCO output signal. These pins are controlled by the µ-controller which has Schmitt Trigger architecture, Internally biased pull-down. The features of these pins are as follows; Clock input for 17 or 19-bit Shift Register, Serial data input (it include TEST1, FRC and LDC), and Latch enable input. In the BS mode (set to Low), the VDD1 block will be powered off, but the internal latch data is still valid because the VDD2 is supplied continuously. This input has Schmitt Trigger architecture & internally biased pull-up. This is the input pin for Fast Locking Control (FLC) which has Schmitt Trigger architecture, Internally biased pull-down. Low = The Current of PDO Charge pump output is Normal (Default: x1) High = The Current of PDO Charge pump output is increase (x 1.5) This is the input pin for TEST which has Schmitt trigger architecture, Internally biased Pull-down. Low = All block will be operated as normal state (Default) High = LD and FL state will be TES mode
10
LD
11 12 13 14
CLK DATA EN BSB
15
FLC
16
TEST
4
PLL FREQUENCY SYNTHESIZER FOR PAGER
S5T8809
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Power Dissipation Operating Temperature Sto.