MODULATION SYSTEM. IS450 Datasheet


IS450 SYSTEM. Datasheet pdf. Equivalent


Part Number

IS450

Description

OPIC LIGHT DETECTOR WITH BULLT-IN SIGNAL PROCESSING CIRCULT FOR LIGHT MODULATION SYSTEM

Manufacture

Sharp Electrionic Components

Total Page 14 Pages
Datasheet
Download IS450 Datasheet


IS450
IS61SP12832
128K x 32 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin LQFP and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
DESCRIPTION
The ICSI IS61SP12832 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the Pentium™, 680X0™, and
PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with ICSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,
BW4 controls DQd, conditioned by BWE being LOW. A LOW
on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP12832 and controlled by the ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
Parameter
tKQ Clock Access Time
tKC Cycle Time
Frenquency
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-117
4
8.5
117
-5 Units
5 ns
10 ns
100 MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SSR011-0B
1

IS450
IS61SP12832
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
A16-A0
17
GW
BWE
BW4
BW3
BW2
BW1
CE
CE2
CE2
OE
2
MODE
CLK Q0
BINARY
COUNTER
CE Q1
A0
A1
CLR
A0’
A1’
DQ
ADDRESS
REGISTER
CE
CLK
15 17
128K x 32
MEMORY
ARRAY
32 32
D DQd Q
BYTE WRITE
REGISTERS
CLK
D DQc Q
BYTE WRITE
REGISTERS
CLK
D DQb Q
BYTE WRITE
REGISTERS
CLK
D DQa Q
BYTE WRITE
REGISTERS
CLK
DQ
ENABLE
REGISTER
CE
CLK
DQ
ENABLE
DELAY
REGISTER
CLK
4
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
32
OE
DQ[31:0]
Integrated Circuit Solution Inc.
SSR011-0B


Features IS61SP12832 128K x 32 SYNCHRONOUS PIPELI NED STATIC RAM FEATURES • Internal se lf-timed write cycle • Individual Byt e Write Control and Global Write • Cl ock controlled, registered address, dat a and control • Pentium™ or linear burst sequence control using MODE input • Three chip enables for simple dept h expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin LQFP and 119-pin PBGA pa ckage • Single +3.3V, +10%, –5% pow er supply • Power-down snooze mode D ESCRIPTION The ICSI IS61SP12832 is a hi gh-speed, low-power synchronous static RAM designed to provide a burstable, hi gh-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ m icroprocessors. It is organized as 131, 072 words by 32 bits, fabricated with I CSI's advanced CMOS technology. The dev ice integrates a 2-bit burst counter, h ighspeed SRAM core, and high-drive capa bility outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-trigg.
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