Document
IS80C51 IS80C31
IS80C51 IS80C31
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER
ISSI
GENERAL DESCRIPTION
® ISSI
®
NOVEMBER 1998
FEATURES
• • • • • • • • • • • • • • • 80C51 based architecture 4K x 8 ROM (IS80C51 only) 128 x 8 RAM Two 16-bit Timer/Counters Full duplex serial channel Boolean processor Four 8-bit I/O ports, 32 I/O lines Memory addressing capability – 64K ROM and 64K RAM Power save modes: – Idle and power-down Six interrupt sources Most instructions execute in 0.3 µs CMOS and TTL compatible Maximum speed: 40 MHz @ Vcc = 5V Industrial temperature available Packages available: – 40-pin DIP – 44-pin PLCC – 44-pin PQFP
The ISSI IS80C51 and IS80C31 are high-performance microcontrollers fabricated using high-density CMOS technology. The CMOS IS80C51/31 is functionally compatible with the industry standard 80C51 microcontrollers. The IS80C51/31 is designed with 4K x 8 ROM (IS80C51 only); 128 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; two 16-bit timer/counters; a six-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS80C51/31 can be expanded using standard TTL compatible memory.
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Figure 1. IS80C51/31 Pin Configuration: 40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC003-1D 11/19/98
1
IS80C51 IS80C31
ISSI
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
®
INDEX P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44
VCC
P1.4
P1.3
P1.2
P1.1
P1.0
NC
43
42
41
40 39 38 37 36 35 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
TOP VIEW
34 33 32 31 30 29
18
WR/P3.6
19
RD/P3.7
20
XTAL2
21
XTAL1
22
GND
23
NC
24
A8/P2.0
25
A9/P2.1
26
A10/P2.2
27
A11/P2.3
28
A12/P2.4
Figure 2. IS80C51/31 Pin Configuration: 44-pin PLCC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC003-1D 11/19/98
IS80C51 IS80C31
P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
ISSI
VCC P1.4 P1.3 P1.2 P1.1 P1.0
®
44 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
NC
39
38
37
36
35
34 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
13
14
15
16
17
18
19
20
21
22
WR/P3.6
RD/P3.7
GND
NC
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
Figure 3. IS80C51/31 Pin Configuration: 44-pin PQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC003-1D 11/19/98
A12/P2.4
XTAL2
XTAL1
3
IS80C51 IS80C31
ISSI
®
P2.0-P2.7
P0.0-P0.7
VCC
P2 DRIVERS
P0 DRIVERS
RAM ADDR REGISTER
ADDRESS DECODER & 128 BYTES RAM
P2 LATCH
P0 LATCH
ADDRESS DECODER & 4K ROM
B REGISTER
STACK POINT
ACC
PROGRAM ADDRESS REGISTER
PCON TL1
SCON TH0
TMOD TCON TL0 TH1
TMP2
TMP1
PROGRAM COUNTER
SBUF IE IP INTERRUPT BLOCK SERIAL PORT BLOCK TIMER BLOCK
ALU
PC INCREMENTER
PSW BUFFER
PSEN ALE RST EA TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR
P3 LATCH OSCILLATOR XTAL1 XTAL2 P3 DRIVERS
P1 LATCH
P1 DRIVERS
P3.0-P3.7
P1.0-P1.7
Figure 4. IS80C51/31 Block Diagram
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC003-1D 11/19/98
IS80C51 IS80C31
Table 1. Detailed Pin Description Symbol ALE PDIP 30 PLCC 33 PQFP 27 I/O I/O Name and Function
ISSI
®
Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. External Access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong .