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IS9108-03CS14 Dataheets PDF



Part Number IS9108-03CS14
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description CPU Frequency Generator
Datasheet IS9108-03CS14 DatasheetIS9108-03CS14 Datasheet (PDF)

Integrated Circuit Systems, Inc. AV9108 CPU Frequency Generator General Description The AV9108 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK1, can vary between 2 and 120 MHz, with up to 16 selectable preprogrammed frequencies stored in internal ROM. The ICS9108 is ideal for use in a 3.3V system. It can generate a 66.66 MHz clock at 3.3V.

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Integrated Circuit Systems, Inc. AV9108 CPU Frequency Generator General Description The AV9108 offers a tiny footprint solution for generating two simultaneous clocks. One clock, the REFCLK, is a fixed output frequency which is the same as the input reference crystal (or clock). The other clock, CLK1, can vary between 2 and 120 MHz, with up to 16 selectable preprogrammed frequencies stored in internal ROM. The ICS9108 is ideal for use in a 3.3V system. It can generate a 66.66 MHz clock at 3.3V. In addition, the ICS9108 provides a symmetrical wave form with a worst case duty cycle of 45/55. The ICS9108 has very tight edge control between the CPU clock and 2XCPU clock outputs, with a worst case skew of 250ps. The device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. A minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter-free operation. Standard versions for computer motherboard applications are the AV9108-03, AV9108-05 and the ICS9108-10. Custom masked versions, with customized frequencies and features, are available in 6-8 weeks for a small NRE fee. Features • • • • • • • • • • • Runs up to 80 MHz at 3.3V 50/50 typical duty cycle at 5V ±250ps absolute jitter Generates frequencies from 2 to 140 MHz 2 to 32 MHz input reference frequency Up to 16 frequencies stored internally Patented on-chip Phase Locked Loop with VCO for clock generation Provides reference clock and synthesized clock On-chip loop filter Low power 0.8µ CMOS technology 8-pin or 14-pin DIP or SOIC package Block Diagram AV 9108 RevB032195 AV9108 Pin Configuration FS0 GND X1/ICLK X2 1 2 3 4 8 7 6 5 REFCLK VDD CLK1 FS1 FS1 FS2 FS3 AGND GND PD X1/ICLK 1 2 3 4 5 6 7 14 13 12 11 10 9 8 FS0 REFCLK VDD CLK1 OE (CLK1) OE (REFCLK) X2 AV9108-05/-10 8-Pin DIP, SOIC AV9108-03/-11 14-Pin DIP, SOIC Pin Descriptions for AV9108-03, AV9108-05 and AV9108-10 PIN NUMBER -05/-10/-13 1 5 -03 14 1 2 3 2 3 4 4 5 6 7 8 9 10 11 12 13 FS0 FS1 FS2 FS3 AGND GMD PD X1/ICLK X2 OE(REFCLK) OE(CLK1) CLK1 VDD REFCLK PIN NAME TYPE Input Input Input Input Input Input Output Input Input Output Output DESCRIPTION Frequency Select 0 for CLK1 (-03 has pull-up). Frequency Select 1 for CLK1 (-03 has pull-up). Frequency Select 2 for CLK1 (-03 has pull-up). Frequency Select 3 for CLK1 (-03 has pull-up). Analog GROUND. Digital GROUND. POWER-DOWN. Shuts off chip when low. Internal pull-up. CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz system clock. CRYSTAL OUTPUT (No Connect when clock used.). OUTPUT ENABLE. Tristates REFCLK when low. Pull-up. OUTPUT ENABLE. Tristates CLK1 when low. Pull-up. CLOCK1 Output (see decoding tables). Digital power supply (+3V DC). REFERENCE CLOCK output. Produces a buffered version of the input clock or crystal frequency (typically 14.318 MHz). 6 7 8 2 AV9108 Actual Frequencies Decoding Table for AV9108-05, 14.318 input FS1 0 0 1 1 FS0 0 1 0 1 CLK1 40.01 MHz 50.11 MHz 66.61 MHz 80.01 MHz Decoding Table for AV9108-11 (in MHz) FS3 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK1 16.00 MHz 33.39 MHz 50.11 MHz 80.01 MHz 66.58 MHz 100.23 MHz 60.00 MHz 4.01 MHz 8.02 MHz 20.05 MHz 25.06 MHz 39.99 MHz 33.25 MHz 50.11 MHz 30.00 MHz 4.01 MHz Decoding Table for AV9108-03, 14.318 input FS3 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK1 16.00 MHz 39.99 MHz 50.11 MHz 80.01 MHz 66.58 MHz 100.23 MHz 8.02 MHz 4.01 MHz 8.02 MHz 20.00 MHz 25.06 MHz 40.01 MHz 33.29 MHz 50.11 MHz 4.01 MHz 2.05 MHz Decoding Table for AV9108-10, 14.318 input FS1 0 0 1 1 FS0 0 1 0 1 CLK1 25.057 MHz 33.289 MHz 40.006 MHz 50.113 MHz Note: The dash number following ICS9108 must be included when ordering product since it specifies the frequency decoding table being ordered. Decoding options can be created by a simple metal mask change. 3 AV9108 Frequency Accuracy and Calculation The accuracy of the frequencies produced by the ICS9108 depends on the input frequency and the desired actual output frequency. The formula for calculating the exact frequency is as follows: Output Frequency = Input Frequency × where A=2, 3, 4 ... 128, and B=2, 3, 4 ... 32. For example, to calculate the actual output frequency for a video monitor expecting a 44.900 MHz clock and using a 14.318 MHz input clock, the closest A/B ratio is 69/22, which gives an output of 44.906 MHz (within 0.02% of the target frequency). Generally, the ICS9108 can produce frequencies within 0.1% of the desired output. A B Allowable Input and Output Frequencies The input frequency should be between 2 and 32 MHz and the A/B ratio should not exceed 24. The output should fall in the range of 2-120 MHz. Output Enable The Output Enable feature tristates the specified output clock pins. This places the selecte.


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