K4S280432A

K4S280432A CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Aug. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S280432A 8M x 4Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 Page ) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S280432A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. K4S280432A-TC/L75 K4S280432A-TC/L80 K4S280432A-TC/L1H K4S280432A-TC/L1L K4S280432A-TC/L10 Max Freq. 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) 66MHz(CL=2 &3) LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM ...