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K4S280432B Dataheets PDF



Part Number K4S280432B
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL
Datasheet K4S280432B DatasheetK4S280432B Datasheet (PDF)

K4S280432B CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Aug. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S280432B 8M x 4Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4 & 8 Page ) -. Burst type (Sequentia.

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K4S280432B CMOS SDRAM 128Mbit SDRAM 8M x 4Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Aug. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S280432B 8M x 4Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4 & 8 Page ) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S280432B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • • • • • ORDERING INFORMATION Part No. K4S280432B-TC/L75 K4S280432B-TC/L80 K4S280432B-TC/L1H K4S280432B-TC/L1L K4S280432B-TC/L10 Max Freq. 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) 66MHz(CL=2 &3) LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE LDQM Data Input Register Bank Select 8M x 4 Sense AMP 8M x 4 8M x 4 8M x 4 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Timing Register Programming Register LWCBR LDQM CLK CKE CS RAS CAS WE DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S280432B PIN CONFIGURATION (Top view) VDD N.C VDDQ N.C DQ0 VSSQ N.C N.C VDDQ N.C DQ1 VSSQ N.C VDD N.C WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS N.C VSSQ N.C DQ3 VDDQ N.C N.C VSSQ N.C DQ2 VDDQ N.C VSS N.C/RFU DQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS CMOS SDRAM 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA 0 ~ CA9, CA11 Selects bank to be activate.


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