K4S280432E

SDRAM 128Mb E-die (x4, x8, x16) CMOS SDRAM 128Mb E-die SDRAM Specification Revision 1.2 May. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 1.2 May. 2003 SDRAM 128Mb E-die (x4, x8, x16) Revision History Revision 1.0 (Nov. 2002) - First release. CMOS SDRAM Revision 1.1 (Apr. 2003) - x4/x8/x16 Merged spec. Revision 1.2 (May. 2003) - Delete -TC(L)7C Rev. 1.2 May. 2003 SDRAM 128Mb E-die (x4, x8, x16) CMOS SDRAM 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4 & 8 ) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for maskin Auto & self refresh 64ms refresh period (4K Cycle) GENERAL DESCRIPTION The K4S280432E / K4S280832E / K4S281632E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable lat...