K4S280432F

SDRAM 128Mb F-die (x4, x8, x16) Preliminary CMOS SDRAM 128Mb F-die SDRAM Specification Revision 0.2 November. 2003 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.2 November. 2003 SDRAM 128Mb F-die (x4, x8, x16) Revision History Revision 0.0 (Agust, 2003) - First release. Revision 0.1 (November, 2003) - completed DC characteristics. Revision 0.2 (November, 2003) - Preliminary spec release. Preliminary CMOS SDRAM Rev. 0.2 November. 2003 SDRAM 128Mb F-die (x4, x8, x16) Preliminary CMOS SDRAM 8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM (x4,x8) & L(U)DQM (x16) for masking Auto & self refresh 64ms refresh period (4K Cycle) GENERAL DESCRIPTION The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every cl...