K4S281632B-N

shrink-TSOP K4S281632B-N 2M x 16Bit x 4 Banks Synchronous DRAM in sTSOP FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S281632B-N is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. K4S281632B-NC/L1H K4S281632B-NC/L1L Max Freq. 100MHz(CL=2) 100MHz(CL=3) Interface Package LVTTL 54pin sTSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 2M x 16 2M x 16 2M x 16 2M x 16 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Prog...