K4S560832C

K4S560832C CMOS SDRAM 256Mbit SDRAM 8M x 8bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 Sept. 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Sept. 2001 K4S560832C Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Sep. 06, 2001) CMOS SDRAM Redefined IDD1 & IDD4 in DC Characteristics Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. Rev. 0.1 Sept. 2001 K4S560832C 8M x 8Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (8K Cycle) Part No. K4S560832C-TC/L7C K4S560832C-TC/L75 K4S560832C-TC/L1H K4S560832C-TC/L1L CMOS SDRAM GENERAL DESCRIPTION The K4S560832C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Sy...