K4S641632C

K4S641632C 1M x 16Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S641632C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. K4S641632C-TC/L60 K4S641632C-TC/L70 K4S641632C-TC/L75 K4S641632C-TC/L80 K4S641632C-TC/L1H K4S641632C-TC/L1L K4S641632C-TC/L10 Max Freq. 166MHz(CL=3) 143MHz(CL=3) 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) 66MHz(CL=3&2) LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 1M x 16 1M x 16 1M x 16 1M x 16 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buf...