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K4X56163PE-LG Dataheets PDF



Part Number K4X56163PE-LG
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 16M x16 Mobile DDR SDRAM
Datasheet K4X56163PE-LG DatasheetK4X56163PE-LG Datasheet (PDF)

K4X56163PE-L(F)G 16M x16 Mobile DDR SDRAM FEATURES Mobile-DDR SDRAM • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 array ) - Internal Temperature Compensated Self Refresh - Driv.

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K4X56163PE-L(F)G 16M x16 Mobile DDR SDRAM FEATURES Mobile-DDR SDRAM • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 3 ) - Burst Length ( 2, 4, 8 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 array ) - Internal Temperature Compensated Self Refresh - Driver strength ( 1, 1/2, 1/4, 1/8 ) • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • LDM/UDM for write masking only. • 7.8us auto refresh duty cycle. • CSP package. Operating Frequency DDR200 Speed @CL3 *CL : CAS Latency DDR133 66Mhz 100Mhz Column address configuration Organization 16Mx16 DM is internally loaded to match DQ and DQS identically. Row Address A0 ~ A12 Column Address A0-A8 1 March 2004 K4X56163PE-L(F)G Package Dimension and Pin Configuration < Bottom View*1 > E1 9 A e B C D A B C D E F G D/2 H J K E E/2 Ball Name 8 7 6 5 4 3 2 1 1 VSS VDDQ VSSQ VDDQ VSSQ VSS CKE A9 A6 VSS Mobile-DDR SDRAM < Top View*2 > 60Ball(6x10) CSP 2 DQ15 DQ13 DQ11 DQ9 UDQS UDM CK A11 A7 A4 3 VSSQ DQ14 DQ12 DQ10 DQ8 N.C. CK A12 A8 A5 7 VDDQ DQ1 DQ3 DQ5 DQ7 N.C. WE CS A10/AP A2 8 DQ0 DQ2 DQ4 DQ6 LDQS LDM CAS BA0 A0 A3 9 VDD VSSQ VDDQ VSSQ VDDQ VDD RAS BA1 A1 VDD D D1 E F G H J K Ball Function System Differential Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input Mask Data Strobe Data Input/Output Power Supply/Ground Data Output Power/Ground *2: Top View CK, CK CS CKE A0 ~ A12 A A1 BA0 ~ BA1 RAS CAS WE Max. 0.20 Encapsulant jb z *1: Bottom View < Top View*2 > #A1 Ball Origin Indicator L(U)DM L(U)DQS DQ0 ~ 15 VDD/VSS VDDQ/VSSQ K4X56163PE-XXXX SAMSUNG Wee k 2 [Unit:mm] Symbol A A1 E E1 D D1 e jb z Min 0.90 0.30 0.40 Typ 0.95 0.35 11.0 6.4 9.0 7.2 0.80 0.45 Max 1.00 0.40 0.50 0.10 March 2004 K4X56163PE-L(F)G Input/Output Function Description SYMBOL CK, CK TYPE Input DESCRIPTION Mobile-DDR SDRAM Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM corresponds to the data on DQ8-DQ15. Bank Address Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register ( mode register or extended mode register ) is loaded during the MODE REGISTER SET command. Data Input/Output : Data bus Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. it is used to fetch write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. No Connect : No internal electrical connection is present. DQ Power Supply : 1.7V to 1.95V. DQ Ground. Power Supply : 1.7V to 1.95V.. Ground. CKE Input CS Input RAS, CAS, WE *1LDM,UDM Input Input BA0, BA1 A [n : 0] Input Input *1DQ *1 I/O.


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