Document
PRELIMINARY
K6R1008C1B-C, K6R1008C1B-I
Document Title
128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial and Industrial Temperature Ranges.
Preliminary PRELIMINARY CMOS SRAM
Revision History
Rev No. Rev. 0.0 Rev.1.0 History Initial release with Design Target. Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary. Release to Final Data Sheet. 2.1. Delete Preliminary. 2.2. Delete 32-SOJ-300 package. 2.3. Delete L-version. 2.4. Delete Data Retention Characteristics and Waveform. 2.5. Add Capacitive load of the test environment in A.C test load. 2.6. Change D.C characteristics. Previous spec. Changed spec. Items (8/10/12ns part) (8/10/12ns part) ICC 160/150/140mA 160/155/150mA ISB 30mA 50mA Draft Data Apr. 1st, 1997 Jun. 1st, 1997 Remark Design Target Preliminary
Rev.2.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Rev 2.0 February 1998
PRELIMINARY
K6R1008C1B-C, K6R1008C1B-I
128K x 8 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 8,10,12ns(Max.) • Low Power Dissipation Standby (TTL) : 50mA(Max.) (CMOS) : 10mA(Max.) Operating K6R1008C1B-8 : 160mA(Max.) K6R1008C1B-10 : 155mA(Max.) K6R1008C1B-12 : 150mA(Max.) • Single 5.0V ±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Center Power/Ground Pin Configuration • Standard Pin Configuration K6R1008C1B-J : 32-SOJ-400 K6R1008C1B-T: 32-TSOP2-400CF
Preliminary PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The K6R1008C1B is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The K6R1008C1B uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1008C1B is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.
ORDERING INFORMATION
K6R1008C1B-C8/C10/C12 K6R1008C1B-I8/I10/I12 Commercial Temp. Industrial Temp.
PIN CONFIGURATION(Top View)
A0
1 2 3 4 5 6 7 8 9
32 A16 31 A15 30 A14 29 A13 28 OE 27 I/O8 26 I/O7
FUNCTIONAL BLOCK DIAGRAM
A1 A2 A3
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7
Pre-Charge Circuit
CS I/O1 I/O2 Vcc
SOJ/ TSOP2
25 Vss 24 Vcc 23 I/O6 22 I/O5 21 A12 20 A11 19 A10 18 17 A9 A8
Row Select
Vss
Memory Array 256 Rows 512x8 Columns
I/O3 10 I/O4 11 WE A4 A5 12 13 14 15 16
I/O1~I/O8
Data Cont. CLK Gen.
I/O Circuit Column Select
A6 A7
PIN FUNCTION
A8 A9 A10 A11 A12 A13 A14 A15 A16
Pin Name A0 - A 16
Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection
CS WE OE
WE CS OE I/O 1 ~ I/O8 VCC VSS N.C
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Rev 2.0 February 1998
PRELIMINARY
K6R1008C1B-C, K6R1008C1B-I
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to V SS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Industrial Symbol VIN, VOUT VCC PD TSTG TA TA Rating -0.5 to 7.0 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -40 to 85 Unit V V W °C °C °C
Preliminary PRELIMINARY CMOS SRAM
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5** Typ 5.0 0 Max 5.5 0 VCC + 0.5*** 0.8 Unit V V V V
* The above parameters are also guaranteed at industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width ≤ 6ns) for I ≤ 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 6ns) for I ≤ 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN = VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, CS=VIH f=0MHz, CS ≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA 8ns 10ns 12ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1** Min -2 -2 2.4 Max 2 2 160 155 15.