K7R163684B

K7R163684B K7R161884B Document Title 512Kx36 & 1Mx18 QDRTM II b4 SRAM 512Kx36-bit,1Mx18-bit QDRTM II b4 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram. 1. Change JTAG Block diagram 1. Add the speed bin (-25) 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 1. Change the Maximum Clock cycle time. 2. Correct the 165FBGA package ball size. 1. Add the power up/down sequencing comment. 2. Update the DC current parameter (Icc and Isb). 3. Change the Max. speed bin from -33 to -30. 1. Change the ISB1. Speed Bin -30 -25 -20 -16 1.0 2.0 1. Final spec release 1. Delete the x8 Org. 2. Delete the 300MHz speed bin 1. Add the 300MHz speed bin 1. Change the stand-by current(ISB1) before after Isb1 -30 : 230 260 -25 : 210 240 -20 : 190 220 -16 : 170 200 From 200 180 160 140 To 230 210 190 170 Oct. 31, 2003 Nov. 28, 2003 Final Final Draft Date Oct. 17. 2002 Dec. 16, 2002 Remark Advance Preliminary 0.2 0.3 0.4 Dec. 26, 2002 Jan. 27, 2003 Mar. 20, 2003 Preliminary Preliminary Preliminary 0.5 April. 4, 2003 Preliminary 0.6 June. 20, 2003 Preliminary 0.7 Oct. 20. 2003 Preliminary 3.0 3.1 June. 18, 2004 July. 28, 2004 Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will eva...