SII161A

SiI 161A PanelLink® Receiver Datasheet General Description The SiI 161A receiver uses PanelLink Digital technology to support high resolution displays up to UXGA. The SiI 161A receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 or 2 pixels/clock mode. In addition, the receiver data output is time staggered to reduce ground bounce that affects EMI. Since all PanelLink products are designed on scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface, system designers can be assured that the interface will be fixed through a number of technology and performance generations. PanelLink Digital technology simplifies PC and display interface design by resolving many of the system level issues associated with high-speed mixed signal design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. March 2001 Features § Low Power: 3.3V core operation Time staggered data output for reduced ground bounce Sync Detect: for Plug & Display “Hot Plugging” Cable Distance Support: over 5m with twisted-pair, fiber-optics ready Compliant with DVI 1.0 (DVI is backwards compatible with VESA ® P&DT M and DFP) Supports Dual-Link operation up to 330 Megapixels/second CONTROLS HSYNC VSYNC OGND OUTPUT CLOCK SiI 161A Pin Diagram GPO OVCC QE23 CTL3 CTL2 CTL1 GND VCC EVEN 8-bits RED OGND OVCC QE22 QE21 QE20 QE19 QE18 QE17 QE16 QE15 QE14 ODCK QO1 QO0 DE ...