SK100E016

8-Bit Synchronous Binary Up Counter HIGH-PER.ORMANCE PRODUCTS Description The SK10/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. The counter features internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to indicate an all-one state. When TCLD is HIGH, the TC* feedback causes the counter to automatically reload upon TC* = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. SK10/100E016 .eatures 700 MHz Min Count Frequency 1000 ps CLK to Q, TC* Internal TC* Feedback (Gated) 8-Bit Fully Synchronous Counting and TC* Generation Asynchronous Master Reset Internal 75 kΩ Input Pulldown Resistors Extended 100E VEE Range of –4.2V to –5.46V Fully Compatible with MC10/100E016 Available in 28-Pin PLCC Package ESD Protection of >4000V .unctional Block Diagram 8 Bit Binary Counter - Logic Counter PE Q0 Q1 Q7 TCLD QOM CE* BIT 0 MASTER QOM* SLAVE Q0* CE* BIT 1 CE* Q0* Q1* Q2* Q3* Q4* Q5* Q6* BIT 7 PO P1 P7 MR CLK BITS 2-6 5 TC* Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate funct...