Binary Up Counter
The SK10/100E016 is a high-speed synchronous, • 700 MHz Min Count Frequency
presettable, cascadable 8-bit binary counter.
• 1000 ps CLK to Q, TC*
• Internal TC* Feedback (Gated)
The counter features internal feedback of TC*, gated by • 8-Bit
the TCLD (terminal count load) pin. When TCLD is LOW • Fully Synchronous Counting and TC* Generation
(or left open, in which case it is pulled LOW by the internal • Asynchronous Master Reset
pull-downs), the TC* feedback is disabled, and counting • Internal 75 kΩ Input Pulldown Resistors
proceeds continuously, with TC* going LOW to indicate • Extended 100E VEE Range of –4.2V to –5.46V
an all-one state. When TCLD is HIGH, the TC* feedback • Fully Compatible with MC10/100E016
causes the counter to automatically reload upon TC* = • Available in 28-Pin PLCC Package
LOW, thus functioning as a programmable counter. The • ESD Protection of >4000V
Qn outputs do not need to be terminated for the count
function to operate properly. To minimize noise and
power, unused Q outputs should be left unterminated.
.unctional Block Diagram
8 Bit Binary Counter - Logic Counter
Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation
delays as many gate functions are achieved internally without incurring a full gate delay.
Revision 1/.ebruary 13, 2001