DatasheetsPDF.com

SK10E016PJ Dataheets PDF



Part Number SK10E016PJ
Manufacturers Semtech Corporation
Logo Semtech Corporation
Description 8-Bit Synchronous Binary Up Counter
Datasheet SK10E016PJ DatasheetSK10E016PJ Datasheet (PDF)

8-Bit Synchronous Binary Up Counter HIGH-PER.ORMANCE PRODUCTS Description The SK10/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. The counter features internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to indicate an all-one state. When TCLD is HIGH, the TC* feedback.

  SK10E016PJ   SK10E016PJ


Document
8-Bit Synchronous Binary Up Counter HIGH-PER.ORMANCE PRODUCTS Description The SK10/100E016 is a high-speed synchronous, presettable, cascadable 8-bit binary counter. The counter features internal feedback of TC*, gated by the TCLD (terminal count load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pull-downs), the TC* feedback is disabled, and counting proceeds continuously, with TC* going LOW to indicate an all-one state. When TCLD is HIGH, the TC* feedback causes the counter to automatically reload upon TC* = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated. SK10/100E016 .eatures • • • • • • • • • • • 700 MHz Min Count Frequency 1000 ps CLK to Q, TC* Internal TC* Feedback (Gated) 8-Bit Fully Synchronous Counting and TC* Generation Asynchronous Master Reset Internal 75 kΩ Input Pulldown Resistors Extended 100E VEE Range of –4.2V to –5.46V Fully Compatible with MC10/100E016 Available in 28-Pin PLCC Package ESD Protection of >4000V .unctional Block Diagram 8 Bit Binary Counter - Logic Counter PE Q0 Q1 Q7 TCLD QOM CE* BIT 0 MASTER QOM* SLAVE Q0* CE* BIT 1 CE* Q0* Q1* Q2* Q3* Q4* Q5* Q6* BIT 7 PO P1 P7 MR CLK BITS 2-6 5 TC* Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay. Revision 1/.ebruary 13, 2001 1 www.semtech.com SK10/100E016 HIGH-PER.ORMANCE PRODUCTS PIN Description Pinout V CCO PE* CE* TC* Function Table P7 P6 P5 25 MR CLK TCLD V EE NC P0 P1 26 27 28 24 23 22 21 20 19 18 17 16 Q7 Q6 V CC Q5 V CCO Q4 Q3 CE* X L L PE* L H H H X X TCLD X L H X X X MR L L L L L H CLK Z Z Z Z ZZ X .unction Load Parallel (Pn to Qn) Continuous Count Count; Load Parallel on TC* = LOW Hold Masters Respond, Slaves Hold Reset (Qn: = LOW, TC*: = HIGH) 28 Lead PLCC 1 (Top View) 2 3 4 5 P2 H X X 15 14 13 12 6 P3 7 P4 8 V CCO 9 Q0 10 Q1 11 Q2 Pin Names Pin P0 - P7 Q0 - Q7 CE* PE* MR CLK TC* TCLD .unction Parallel Data (Preset) Inputs Data Outputs Count Enable Control Input Parallel Load Enable Control Input Master Reset Clock Terminal Count Output TC-Load Control Input Revision 1/.ebruary 13, 2001 2 www.semtech.com SK10/100E016 HIGH-PER.ORMANCE PRODUCTS Application Information Function Table .unct i on Load Count PE * L H H H H Load Ho l d L o a d On Ter minal Count L H H H H H H H H Reset X CE * X L L L L X H H L L L L L L X MR L L L L L L L L L L L L L L H T CL D X L L L L X X X H H H H H H X CL K Z Z Z Z Z Z Z Z Z Z Z Z Z Z X P7- P4 H X X X H H X X H H H H H H X P3 H X X X H H X X L L L L L L X P2 H X X X H H X X H H H H H H X P1 L X X X L L X X H H H H H H X P0 L X X X L L X X L L L L L L X Q7 - Q4 H H H H H H H H H H H H H H L Q3 H H H H H H H H H H H L L H L Q2 H H H H H H H H H H H H H L L Q1 L L H H L L L L L H H H H L L Q0 L H L H L L L L H L H L H L L TC H H H L H H H H H H L H H H G Cascading Multiple E016 Devices For applications which call for larger than 8-bit counters, multiple E016s can be tied together to achieve very wide bit width counters. The active low terminal count (TC*) output and count enable input (CE*) greatly facilitate the cascading of E016 devices. Two E016s can be cascaded without the need for external gating; however, for counters wider than 16 bits, external OR gates are necessary for cascade implementations. Figure 3 below illustrates the cascading of 4 E016s to build a 32-bit high frequency counter. Note that the E101 gates are used to OR the terminal count outputs of the lower order E016s to control the counting operation of the higher order bits. When the terminal count of the preceding device (or devices) goes low (the counter reaches an all 1s state), the more significant E016 is set in its count mode and will count one binary digit upon the next positive clock transition. In addition, the preceding devices will also count one bit, sending their terminal count outputs back to a high state, disabling the count operation of the more significant counters, and placing them back into hold modes. Therefore, for an E016 in the chain to count, Revision 1/.ebruary 13, 2001 all of the lower order terminal count outputs must be in the low state. The bit width of the counter can be increased or decreased by simply adding or subtracting E016 devices from Figure 3 and maintaining the logic pattern illustrated in the same figure. The maximum frequency of operation for the cascaded counter chain is set by the propagation delay of the TC* output, the necessary setup time of the CE* input, and the propagation delay through the OR gate controlling it (for 16-bit counters the limitation is only the TC* propagation delay and the CE* setup time). Figure 3 shows EL01 gates used to control the count enable inputs.


SK10E016 SK10E016PJ SK10E016PJT


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)