Logarithmic Amplifier. SL2524 Datasheet


SL2524 Amplifier. Datasheet pdf. Equivalent


SL2524


1.3GHz Dual Wideband Logarithmic Amplifier
SL2524
1.3GHz Dual Wideband Logarithmic Amplifier
DS4548 - 2.1 July 1995

The SL2524 is a pin compatible replacement for the SL2521 and SL2522 series of log amplifiers, and exhibits a superior stability performance. The amplifier is a successive detection type which provides linear gain and accurate logarithmic signal compression over a wide bandwidth. The two stages can be operated independently. When six stages (three SL2524s) are cascaded the strip can be used for IFs between 30-650MHz whilst achieving greater than 65dB dynamic range with a log accuracy of <±1.0dB. The balanced limited output also offers accurate phase information with input amplitude.

FEATURES
s s s s s s 1.3GHz Bandwidth (-3dB) Balanced IF limiting 3ns Rise Times/5ns Fall Times (six stages) 20ns Pulse Handling (six stages) Temperature Stabilised Surface Mountable

APPLICATIONS
s s s Ultra Wideband Log Receivers Channelised Receivers Monopulse Applications
OPTIONAL PIN REFERENCE

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC above VEE) +7.0V Storage temperature -65°C to +150°C Operating temperature range SL2524/B/LC -40°C to +85°C SL2524/C/HP -30°C to +85°C Junction temperature - LC20 +175°C - HP20 +150°C Applied DC voltage to RF input ±0.4V (between RF I/P pins) Applied RF power to RF input +15dBm NOT less than 180Ω Value of RSET resistors Thermal resistance:Die to case -LC 20 28°C/W - HP20 20°C/W Die to a...



SL2524
SL2524
1.3GHz Dual Wideband Logarithmic Amplifier
DS4548 - 2.1 July 1995
The SL2524 is a pin compatible replacement for the
SL2521 and SL2522 series of log amplifiers, and exhibits a
superior stability performance. The amplifier is a successive
detection type which provides linear gain and accurate loga-
rithmic signal compression over a wide bandwidth. The two
stages can be operated independently.
When six stages (three SL2524s) are cascaded the strip
can be used for IFs between 30-650MHz whilst achieving
greater than 65dB dynamic range with a log accuracy of
<±1.0dB. The balanced limited output also offers accurate
phase information with input amplitude.
FEATURES
s 1.3GHz Bandwidth (-3dB)
s Balanced IF limiting
s 3ns Rise Times/5ns Fall Times (six stages)
s 20ns Pulse Handling (six stages)
s Temperature Stabilised
s Surface Mountable
APPLICATIONS
s Ultra Wideband Log Receivers
s Channelised Receivers
s Monopulse Applications
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC above VEE)
+7.0V
Storage temperature
-65°C to +150°C
Operating temperature range
SL2524/B/LC
-40°C to +85°C
SL2524/C/HP
-30°C to +85°C
Junction temperature - LC20
+175°C
- HP20
+150°C
Applied DC voltage to RF input ±0.4V (between RF I/P
pins)
Applied RF power to RF input
+15dBm
Value of RSET resistors
Thermal resistance:-
NOT less than 180
Die to case -LC 20
28°C/W
- HP20
20°C/W
Die to ambient - LC20
73°C/W
- HP20
82°C/W
ORDERING INFORMATION
SL2524/B/LC (Ceramic leadless chip carrier package)
SL2524/C/HP (Plastic J lead chip carrier package)
SL2524/NA/1C (DC probe tested bare die)
5962 - 92315 (SMD)
OPTIONAL PIN
REFERENCE
PIN DESCRIPTION
PIN DESCRIPTION
1 SUB VEE
2 IF OUTPUT (A)
11 N/C
12 R SET (B)
3 IF OUTPUT (A)
13 DET. OUTPUT (B)
4 VEE (A)
5 OUTPUT VC (A)
6 IF INPUT (A)
14 VCC (B)
15 IF OUTPUT (B)
16 IF OUTPUT (B)
7 IF INPUT (A)
17 OUTPUT VCC (B)
8 V (A)
CC
18 VEE (B)
9 DET. OUTPUT (A) 19 IF INPUT (B)
10 R SET (A)
20 IF INPUT (B)
Fig.1 Pin connections top view

SL2524
SL2524
Fig.2 Circuit diagram of single stage A - (stage B pin Nos bracketed)
Fig.3 Pad map for SL2524 naked die
2




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