Document
Si6924AEDQ
Vishay Siliconix
N-Channel 2.5-V (G-S) Battery Switch, ESD Protection
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
0.033 at VGS = 4.5 V 28 0.038 at VGS = 3.0 V
0.042 at VGS = 2.5 V
ID (A) 4.6 4.3 4.1
FEATURES
• Halogen-free • Low RDS(on) • VGS Max Rating: 14 V • Exceeds 2 kV ESD Protection
• 28 V VDS Rated • Symmetrical Voltage Blocking (Off Voltage)
RoHS
COMPLIANT
DESCRIPTION
The Si6924AEDQ is a dual N-Channel MOSFET with ESD protection and gate over-voltage protection circuitry incorporated into the MOSFET. The device is designed for use in Lithium Ion battery pack circuits. The common-drain construction takes advantage of the typical battery pack topology, allowing a further reduction of the device’s onresistance. The 2-stage input protection circuit is a unique design, consisting of two stages of back-to-back zener diodes separated by a resistor. The first stage diode is designed to absorb most of the ESD energy. The second
stage diode is designed to protect the gate from any remaining ESD energy and over-voltages above the gates inherent safe operating range. The series resistor used to
limit the current through the second stage diode during over voltage conditions has a maximum value which limits the input current to ≤ 10 mA at 14 V and the maximum toff to 12 µs. The Si6924AEDQ has been optimized as a battery or load switch in Lithium Ion applications with the advantage of both a 2.5 V RDS(on) rating and a safe 14 V gate-to-source maximum rating.
APPLICATION CIRCUITS
ESD and Overvoltage Protection
ESD and Overvoltage Protection
Battery Protection Circuit *Thermal connection to drain pins is required to achieve specific performance
Figure 1. Typical Use In a Lithium Ion Battery Pack
R** G
D
S
**R typical value is 3.3 kΩ by design. See Typical Characteristics,
Gate-Current vs. Gate-Source Voltage, Page 3.
Figure 2. Input ESD and Overvoltage Protection Circuit
Document Number: 72215 S-81056-Rev. B, 12-May-08
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Si6924AEDQ
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
*D *D
TSSOP-8
D1 S1 2 S1 3 G1 4
Si6924AEDQ
8D 7 S2 6 S2 5 G2
Top View
Ordering Information: Si6924AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free)
3.3 kΩ G1
3.3 kΩ G2
S1 N-Channel
S2 N-Channel
*Thermal connection to drain pins is required to achieve specific performance.
Figure 3.
Figure 4.
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
10 s
Steady State
Drain-Source Voltage, Source-Drain Voltage
VDS 28
Gate-Source Voltage
VGS ± 14
Continuous Drain-to-Source Current (TJ = 150 °C)a
TA = 25 °C TA = 70 °C
ID
4.6 4.1 3.7 3.2
Pulsed Drain-to-Source Current
IDM 20
Pulsed Source Current (Diode Conduction)a
IS 1.2 0.9
Maximum Power Dissipationa
TA = 25 °C TA = 70 °C
PD
1.3 1.0 0.84 0.64
Operating Junction and Storage Temperature Range
TJ, Tstg
- 55 to 150
Unit V
A
W °C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain) Notes: a. Surface Mounted on FR4 board.
t ≤ 10 s Steady State Steady State
Symbol RthJA RthJF
Typical 71 96 56
Maximum 95 125 70
Unit °C/W
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Document Number: 72215 S-81056-Rev. B, 12-May-08
Si6924AEDQ
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Currentb
Drain-Source On-State Resistanceb
Forward Transconductanceb Diode Forward Voltageb Dynamica Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time
VGS(th) IGSS
IDSS ID(on)
RDS(on)
gfs VSD
Qg Qgs Qgd td(on)
tr td(off)
tf
VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 4.5 V VDS = 0 V, VGS = ± 14 V VDS = 22.4 V, VGS = 0 V VDS = 22.4 V, VGS = 0 V, TJ = 55 °C
VDS ≥ 5 V, VGS = 5 V VGS = 4.5 V, ID = 4.6 A VGS = 3.0 V, ID = 4.3 A VGS = 2.5 V, ID = 4.1 A VDS = 10 V, ID = 4.6 A IS = 1.2 A, VGS = 0 V
VDS = 10 V, VGS = 4.5 V, ID = 4.6 A
VDD = 10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 4.5 V, RG = 6 Ω
Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Min. 0.6
10
Typ.
Max.
1.5 ±1 ± 20 1 5
0.022 0.025 0.029
25 0.7
0.033 0.038 0.042
1.1
Unit
V µA mA µA A
Ω
S V
6.5 1.2 1.5 0.95 1.4 7 3.1
10
1.5 2.1 11 5
nC µs
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.020
10,000
I GSS - Gate Current (mA) I GSS - Gate Current (A)
0.015 0.010
1,000 100 10 1
TJ = 150 °C
0.005
0.1
TJ = .