Voltage Supervisor. MIC1832 Datasheet

MIC1832 Supervisor. Datasheet pdf. Equivalent

Part MIC1832
Description 3.3V Voltage Supervisor
Feature MIC1832 3.3V Voltage Supervisor with Manual Reset, Watchdog Timer and Dual Reset Outputs General De.
Manufacture Micrel Semiconductor
Total Page 7 Pages
Datasheet
Download MIC1832 Datasheet



MIC1832
MIC1832
3.3V Voltage Supervisor with Manual Reset,
Watchdog Timer and Dual Reset Outputs
General Description
The MIC1832 is a low-current microprocessor supervisor
for monitoring 3.3V and 3V systems. The device features
logic-selectable (TOL) reset thresholds of 10% or 20% of
3.3V; a pushbutton reset input; a watchdog timer with
three-state selectable (TD) timeout periods of 150ms,
600ms, or 1.2s; a fixed reset timeout period of 250ms
(min); and active-low open-drain reset (/RST) and active-
high push-pull reset (RST) outputs. The /RST output
maintains a valid reset condition for VCC as low as 1.4V.
The MIC1832 asserts a reset condition if the supply
voltage drops below the reset threshold, the pushbutton
reset is asserted low, or the watchdog timer does not see
a high-to-low transition on the watchdog timer input within
the watchdog timer period. A reset condition is held for the
reset timeout period of 250ms (min) after the pushbutton
input is released, after the supply voltage increases above
the reset threshold voltage, or after the watchdog has
initiated a reset.
The MIC1832 is a drop-in replacement for the DS1832. It
operates over the –40°C to +85°C temperature range and
is available in Pb-Free 8-pin SOIC and PDIP packages.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
Features
Low-current version of DS1832
Low current: 15µA (typ), 25µA (max)
Selectable threshold (TOL): 10% or 20% of 3.3V
Selectable watchdog timer (TD): 150ms, 600ms, 1.2s
Power OK/Reset time delay: 250ms (min)
Debounced pushbutton reset input
Dual complementary reset outputs
o Active-low, open-drain reset output
o Active-high, push-pull reset output
Available in Pb-Free 8-pin SOIC and PDIP packages
–40°C to +85°C temperature range
Pin-for-Pin compatible with MIC1232/DS1232/CAT1232
Applications
Automotive systems
Intelligent systems
Critical microprocessor power monitoring
Battery powered computers
Controllers
_________________________________________________________________________________________________________________________
Typical Application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
February 2013
M9999-020413



MIC1832
Micrel, Inc.
Ordering Information
Part Number
MIC1832NY
MIC1832MY
Temperature Range
–40° to +85°C
–40° to +85°C
Pin Configuration
Package
8-Pin PDIP
8-Pin SOIC
Lead Finish
Pb-Free
Pb-Free
MIC1832
8-Pin PDIP
8-Pin SOIC
Pin Description
Pin Number
1
Pin Name
/PBRST
2 TD
3 TOL
4 GND
5 RST
6 /RST
7 /ST
8 VCC
Pin Function
Pushbutton Reset input: This input is debounced and can be driven with external logic signals or by
using a mechanical pushbutton to actively force a reset. All pulses less than 1ms in duration on the
/PBRST pin are ignored; any pulse with a duration of 20ms or greater is guaranteed to cause a
reset.
Time Delay input: This input selects the timebase used by the watchdog timer. When TD = 0V, the
watchdog timeout period is set to a normal value of 150ms. When TD = open, the watchdog timeout
period is set to a nominal value of 600ms. When TD = VCC, the watchdog period is 1.2s nominally.
Tolerance Select input: This input selects whether 10% or 20% of VCC is used as the reset
threshold voltage. When TOL = 0V, the 10% tolerance level is selected and when TOL = VCC, a
20% tolerance level is selected.
IC ground pin, 0V reference
RST is asserted high if either VCC goes below the reset threshold, the watchdog times out, or
/PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout period
after VCC exceeds the reset threshold, after the watch times out, or after /PBRST goes high.
/RST is asserted low if either VCC goes below the reset threshold, the watchdog times out, or
/PBRST is pulled low for a minimum of 20ms. /RST remains asserted for one reset timeout period
after VCC exceeds the reset threshold, after the watch times out, or after /PBRST goes high. Open-
drain output
Input to watchdog timer. If /ST does not see a transition from high to low within the watchdog
timeout period, RST and /RST are asserted.
Primary supply input.
February 2013
2 M9999-020413





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