Document
200mA & 250mA SmartLDOsTM
POWER MANAGEMENT Description
The SC1531(A) is designed to maintain a glitch-free 3.3V output when at least one of two inputs, 5V (VIN) and 3.3V (VAUX), is present.
SC1531(A)
Features
Glitch-free transition between input sources Internal logic selects input source Gate drive for external PMOS bypass switch 5V detection with hysteresis 1% regulated output voltage accuracy 200mA load current capability (250mA for SC1531A) Remote sense SO-8 package
u u u u Whenever VIN exceeds a predetermined threshold value, u the internal 3.3V linear regulator is enabled, and DR is u pulled high. u When VIN falls below a lower threshold value, DR is pulled u
low and the internal linear regulator is turned off. DR has been designed to drive the gate of an external low threshold P-channel MOSFET, which can be used to connect the 3.3V supply directly to the regulator output. This ensures an uninterrupted 3.3V output even if VIN falls out of specification. A typical RDS(ON) of 400mW is recommended (320mW for SC1531A). When both supplies are simultaneously available, the drive pin (DR) will be pulled High, turning off the external PMOS switch. The internal 5V detector has its upper threshold (for VIN rising) set to 4.18V (typical) while the lower threshold (for VIN falling) is at 4.05V (typical) giving a hysteresis of approximately 130mV. The SENSE pin, which is connected to the load, connects internally to the inverting input of the LDO error amplifier. It enables tight regulation of the load voltage (while the 5V supply is present) despite variations in load current. The SC1531(A) is available in the popular SO-8 surface mount package.
Applications
u u u u u
Desktop Computers Network Interface Cards (NICs) PCMCIA/PCI Interface Cards CardbusTM Technology Power supplies with multiple input sources
Typical Application Circuit
Notes for Typical Application Circuit: (1) External switch (Q1): use Motorola MGSF1P02ELT1 or equivalent (PMOS, typical Gate Threshold Voltage = 1V, typical RDS(ON) = 0.4W at VGS = 2.5V) for SC1531. Use Vishay Si2301DS or equivalent for SC1531A. (2) Connection of VAUX (pin 3) is optional.
Q1
U1 5V 3.3V 1 2 3 4 C1 0.1uF C2 4.7uF C3 0.1uF VIN DR NC VO VAUX SENSE GND NC SC1531 8 7 6 5 C4 4.7uF C5 0.1uF 3.3V OUT
Revision 1, December 2000
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SC1531(A)
POWER MANAGEMENT Absolute Maximum Rating
Parameter Input Supply Voltage Auxi li ary Supply Voltage LD O Output C urrent (SC 1531) LD O Output C urrent (SC 1531A) Thermal Impedance Juncti on to Ambi ent Thermal Impedance Juncti on to C ase Operati ng Ambi ent TemperatureRange Operati ng Juncti on Temperature Range Storage Temperature Range Lead Temperature (Solderi ng) 10 Sec. ESD Rati ng Sy mbol VIN VAUX IO IO q JA q JC TA TJ TSTG TLEAD V ESD Maximum -0.5 to +7 -0.5 to +7 200 250 130 47 -5 to +70 -5 to +125 -65 to +150 300 2 U nits V V mA mA °C /W °C /W °C °C °C °C kV
Electrical Characteristics
Unless specified: TA = 25°C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7µF. Values in bold apply over full operating temperature range.
Parameter VIN Supply Voltage Qui escent C urrent
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
VIN IQ
VAUX = 0V VIN = 5V, VAUX = 0V, IO = 0mA
4.3
5.0 7.0
5.5 10.0 11.0
V mA
VIN = 5V, VAUX = 3.3V, IO = 0mA
7.5
10.0 12.0
mA
Reverse Leakage From VAUX
IVIN
VAUX = 3.6V, VIN = 0V, IO = 0mA
1.0
10 20
µA
VAU X Supply Voltage Qui escent C urrent VAUX IQ(AUX) VAUX = 3.3V, VIN = 0V, IO = 0mA 3.0 3.3 0.8 3.6 1.5 2.0 VAUX = 3.3V, VIN = 5V, IO = 0mA 0.6 1.0 2.0 Reverse Leakage From VIN IVAUX VIN = 5.5V, VAUX = 0V, IO = 0mA 7 50 100
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V mA
mA
µA
SC1531(A)
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25°C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7µF. Values in bold apply over full operating temperature range.
Parameter 5V D etect(1)(2)(3) Low Threshold Voltage Hysteresi s
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
VTH(LO) VHYST
VIN Falli ng
3.90 90 80
4.05 200
4.20
V mV
Hi gh Threshold Voltage VO LD O Output Voltage
VTH(HI)
VIN Ri si ng
4.30
V
VO
IO = 20mA 4.3V £ VIN £ 5.5V, 0mA £ IO £ IO(MAX) 3.9V £ VIN £ 4.3V, VAUX = 3.3V, 0mA £ IO £ IO(MAX)(4)
3.267 3.234 3.000
3.300
3.333 3.366
V
Li ne Regulati on
REG(LINE)
VIN = 4.3V to 5.5V
0.12
0.40 0.60
%
Load Regulati on
REG(LOAD)
IO = 20mA to IO(MAX)
0.12
0.40 0.60
%
SEN SE SENSE Pi n Impedance DR D ri ve Voltage V DR 4.3V £ VIN £ 5.5V, IDR = 200µA 3.4 3.3 VIN < VTH(LO), IDR = -200µA 35 150 200 Peak D ri ve C urrent IDR(PK) Si nki ng: VIN = 3.9V, VDR = 1V; Sourci ng: VIN = 4.3V, (VIN - VDR) = 2V D ri ve Hi gh D elay(1)(5) tDH C DR = 1.2nF, VIN rampi ng up, measured from VIN = VTH(HI) to VDR = 2V D ri ve Low D elay(1)(5) tDL C DR = 1.2nF, VIN rampi ng down, measured from VIN = VTH(LO) to VDR = 2V 0.5 7 6 0.5 1.0 2.0 1.0 2.0 µs µs mA mV VIN - 0.8 V RSENSE 6.0 8.5 kW
See next page for Notes.
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