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SCAN18373T Dataheets PDF



Part Number SCAN18373T
Manufacturers National Semiconductor
Logo National Semiconductor
Description Transparent Latch with TRI-STATE Outputs
Datasheet SCAN18373T DatasheetSCAN18373T Datasheet (PDF)

SCAN18373T Transparent Latch with TRI-STATE Outputs September 1998 SCAN18373T Transparent Latch with TRI-STATE ® Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and t.

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SCAN18373T Transparent Latch with TRI-STATE Outputs September 1998 SCAN18373T Transparent Latch with TRI-STATE ® Outputs General Description The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). Features n n n n n n n n n n IEEE 1149.1 (JTAG) Compliant Buffered active-low latch enable TRI-STATE outputs for bus-oriented applications 9-bit data busses for parity applications Reduced-swing outputs source 24 mA/sink 48 mA Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V TTL compatible inputs 25 mil pitch Cerpack packaging Includes CLAMP and HIGHZ instructions Standard Microcircuit Drawing (SMD) 5962-9311801 Connection Diagram Pin Names AI(0–8), BI(0–8) ALE, BLE AOE1, BOE1 AO(0–8), BO(0–8) Description Data Inputs Latch Enable Inputs TRI-STATE Output Enable Inputs TRI-STATE Latch Outputs Truth Tables Inputs ALE X H H L AOE1 H L L L Inputs BLE X H H L BOE1 H L L L BI (0–8) X L H X Z L H BO0 AI (0–8) X L H X Z L H AO0 BO (0–8) AO (0–8) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE Functional Description DS100321-1 The SCAN18373T consists of two sets of nine D-type latches with TRI-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI(0–8) or BI(0–8) ) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW transition of the TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100321 www.national.com Functional Description (Continued) Latch Enable. The TRI-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. Logic Diagram DS100321-13 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A DS100321-2 www.national.com 2 Block Diagrams (Continued) Tap Controller DS100321-3 Byte-B DS100321-4 Note 1: BSR stands for Boundary Scan Register. 3 www.national.com Description of Boundary-Scan Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 for a further description of scan cell TYPE1 and for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 DS100321-10 The INSTRUCTION register is an eight-bit register which captures the value 00111101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition MSB → LSB Instruction Code 00000000 DS100321-9 Instruction EXTEST SAMPLE/PRELOAD CLAMP HIGHZ BYPASS 10000001 10000010 00000011 All Others Scan Cell TYPE1 DS100321-7 www.national.com 4 Description of Boundary-Scan Circuitry (Continued) Scan Cell TYPE2 DS100321-8 5 www.national.com Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (42 Bits in Length) DS100321-25 www.national.com 6 Description of Boundary-Scan Circuitry Bit No. 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 2.


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