Document
INTEGRATED CIRCUITS
DATA SHEET
SAF7113H 9-bit video input processor
Product specification File under Integrated Circuits, IC22 2000 May 08
Philips Semiconductors
Product specification
9-bit video input processor
CONTENTS 1 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 9.1 9.2 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Analog input processing Analog control circuits Chrominance processing Luminance processing Synchronization Clock generation circuit Power-on reset and CE input Multi-standard VBI data slicer VBI-raw data bypass Digital output port VPO7 to VPO0 RTCO output RTS0, RTS1 terminals BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes 10 11 12 13 13.1 14 15 15.1 15.2 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 LIMITING VALUES
SAF7113H
THERMAL CHARACTERISTICS CHARACTERISTICS TIMING DIAGRAMS Errata information APPLICATION INFORMATION I2C-BUS DESCRIPTION I2C-bus format I2C-bus detail I2C-BUS START SET-UP PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2000 May 08
2
Philips Semiconductors
Product specification
9-bit video input processor
1 FEATURES
SAF7113H
• Four analog inputs, internal analog source selectors, e.g. 4 × CVBS or 2 × Y/C or (1 × Y/C and 2 × CVBS) • Two analog preprocessing channels in differential CMOS style for best S/N-performance • Fully programmable static gain or automatic gain control for the selected CVBS or Y/C channel • Switchable white peak control • Two built-in analog anti-aliasing filters • Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C-signals are available on the VPO-port via I2C-bus control • On-chip clock generator • Line-locked system clock frequencies • Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection • Requires only one crystal (24.576 MHz) for all standards • Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards • Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43, NTSC-Japan and SECAM • User programmable luminance peaking or aperture correction • Cross-colour reduction for NTSC by chrominance comb filtering • PAL delay line for correcting PAL phase errors • Brightness Contrast Saturation (BCS) and hue control on-chip • Real-time status information output (RTCO) • Two multi functional real-time output pins controlled by I2C-bus • Multi-standard VBI-data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), closed caption, Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. • Standard ITU 656 YUV 4 : 2 : 2 format (8-bit) on VPO output bus • Enhanced ITU 656 output format on VPO output bus containing: – active video – raw CVBS data for INTERCAST applications (27 MHz data rate) – decoded VBI data • Boundary scan test circuit complies with the “IEEE Std. 1149.b1 - 1994” (ID-Code = 1 7113 02B) • I2C-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s) • Low power (<0.5 W), low voltage (3.3 V), small package (QFP44) • Power saving mode by chip enable input • Detection of copy protected input signals according to the macrovision standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals. 2 APPLICATIONS
• Notebook (low power consumption) • PCMCIA card application • AGP based graphics cards • Image processing • Video phone applications • Intercast and PC teletext applications • Security applications.
2000 May 08
3
Philips Semiconductors
Product specification
9-bit video input processor
3 GENERAL DESCRIPTION
SAF7113H
The integrated high performance multi-standard data slicer supports several VBI data standards: • Teletext [WST (World Standard Teletext), CCST (Chinese teletext)] (625 lines) • Teletext [US-WST, NABTS (North-American Broadcast Text System) and MOJI (Japanese teletext)] (525 lines) • Closed caption [Europe, US (line 21)] • Wide Screen Signalling (WSS) • Video Programming Signal (VPS) • Time codes (VITC EBU/SMPTE) • HIGH-speed VBI data bypass for intercast application.
The 9-bit video input processor is a combination of a two-channel analog preprocessing circuit including source selection, anti-aliasing filter and ADC, an automatic clamp and gain control, a Clock Generation Circuit (CGC), a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N and SECAM), a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 M.