Document
56F8322/56F8122
Data Sheet Preliminary Technical Data
56F8300 16-bit Hybrid Controllers
MC56F8322 Rev. 10.0 10/2004
freescale.com
Document Revision History
Version History Rev 1.0 Rev 2.0 Rev 3.0 Description of Change Pre-Release version, Alpha customers only Initial Public Release Corrected typo in Table 10-4, Flash Endurance is 10,000 cycles. Addressed additional grammar issues Added Package Pins to GPIO table in Section 8. Clarification of TRST usage in this device. Replacing TBD Typical Min with values in Table 10-17. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters, Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing, Table 10-18, ADC Parameters, Table 10-24, and IO Loading Coefficients at 10MHz, Table 10-25 Updated values in Power-On Reset Low Voltage Table 10-6. Added Section 4.8 , added addition text to Section 6.9 on POR reset, added the word “access” to FM Error Interrupt in Table 4-3, removed min and max numbers; only documenting Typ. numbers for LVI in Table 10-6. Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in Table 10-3 in Pd characteristics Replace any reference to Flash Interface Unit with Flash Memory Module; corrected typo on page 1 for ADC channel; changed example in Section 2.2 ; added note on VREFHand VREFLO in Table 2-2 and Table 11-1; corrected typo FIVAL1 and FIVAH1 in Table 4-12; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-20. Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1. Added 56F8122 information; edited to indicate differences in 56F8322 and 56F8122. Reformatted to reflect Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Rev 4.0
Rev 5.0 Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev. 10.0
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8322 Techncial Data, Rev. 10.0 2 Freescale Semiconductor Preliminary
56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 32KB Program Flash • 4KB Program RAM • 8KB Data Flash • 8KB Data RAM • 8KB Boot Flash • One 6-channel PWM module • Two 3-channel 12-bit ADCs • Temperature Sensor • One Quadrature Decoder • FlexCAN module • Up to two Serial Communication Interfaces (SCIs) • Up to two Serial Peripheral Interfaces (SPIs) • Two general-purpose Quad Timers • Computer Operating Properly (COP)/Watchdog • On-Chip Relaxation Oscillator • JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging • Up to 21 GPIO lines • 48-pin LQFP Package
RESET 4 6
VCAP 2
VDD 4 4
VSS
VDDA
VSSA
PWM Outputs Fault Inputs
PWMA or SPI1 or GPIOA
Program Controller and Hardware Looping Unit
JTAG/ EOnCE Port
Digital Reg
Analog Reg
16-Bit 56800E Core
Low Voltage Supervisor Bit Manipulation Unit
Address Generation Unit
Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators
3 3 3
AD0 AD1
VREF TEMP_SENSE
PAB PDB CDBR CDBW
Memory
Program Memory 16K x 16 Flash 2K x 16 RAM 4K x 16 Boot Flash Data Memory 4K x 16 Flash 4K x 16 RAM
XDB2 XAB1 XAB2 PAB PDB CDBR CDBW
R/W Control
System Bus Control
4
Quadrature Decoder 0 or Quad Timer A or GPIO B
IPBus Bridge (IPBB)
2 Quad Timer C or SCI0 or GPIOC FlexCAN or GPIOC Peripheral Device Selects RW Control IPWDB IPRDB
2
Decoding Peripherals
Clock resets
PLL
SPI0 or SCI1 or GPIOB 4
COP/ Watchdog
Interrupt Controller
System P O Integration R Module
O Clock S Generator* C
XTAL or GPIOC EXTAL or GPIOC
IRQA
*Includes On-Chip Relaxation Oscillator
56F8322/56F8122 Block Diagram
56F8322 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 3
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8322/56F8122 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . 8 Architecture Block Diagram . . . . . . . . . . . . . 9 Product Documentation . . . . . . . . . . . . . . . 13 Data Sheet Conventions . . . . . . . . . . . . . . . 13
Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .96 8.2. Configuration . . . . . . . . . . . . . . . . . . . . . . . .96 8.3. Memory Maps . . . . . . . . . . . . . . . . . . . . . . . .98
Part 9: Joint Test Action Group (JTAG) . . . 98
9.