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ISP1032E Dataheets PDF



Part Number ISP1032E
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description High-Density Programmable Logic
Datasheet ISP1032E DatasheetISP1032E Datasheet (PDF)

ispLSI and pLSI 1032E ® ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasabl.

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ispLSI and pLSI 1032E ® ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — In-System Programmable (ISP™) 5-Volt Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispLSI DEVELOPMENT TOOLS ispVHDL™ Systems — VHDL/Verilog-HDL/Schematic Design Options — Functional/Timing/VHDL Simulation Options ispDS™ Software — Lattice HDL or Boolean Logic Entry — Functional Simulator and Waveform Viewer ispDS+™ HDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation — Static Timing Analyzer ISP Daisy Chain Download Software Functional Block Diagram Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 A0 D Q C7 Output Routing Pool A2 A3 A4 A5 A6 A7 D Q Logic Array C5 D Q GLB C4 C3 D Q C2 C1 Global Routing Pool (GRP) B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool C0 CLK Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E features 5-Volt in-system programmability and in-system diagnostic capabilities. The ispLSI 1032E device offers non-volatile reprogrammability of the logic, as well as the interconnects to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1032 architecture, the ispLSI and pLSI 1032E devices add two new global output enable pins. The basic unit of logic on the ispLSI and pLSI 1032E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the i.


IS24C64-2 ISP1032E ITM1602ASTL


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