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ICS84314AYLFT Dataheets PDF



Part Number ICS84314AYLFT
Manufacturers Integrated Circuit Systems
Logo Integrated Circuit Systems
Description 350MHZ/ CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Datasheet ICS84314AYLFT DatasheetICS84314AYLFT Datasheet (PDF)

Integrated Circuit Systems, Inc. ICS84314 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER FEATURES • Fully integrated PLL • 4 differential 3.3V or 2.5V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS TEST_CLK input • Output frequency range: 62.5MHz to 350MHz • VCO range: 250MHz to 700MHz • Parallel interface for programming counter and output dividers during power-up • Serial 3 wire interface • Cycle-to-cycle jitter: 23ps (typical) • Output skew: 16p.

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Integrated Circuit Systems, Inc. ICS84314 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER FEATURES • Fully integrated PLL • 4 differential 3.3V or 2.5V LVPECL outputs • Selectable crystal oscillator interface or LVCMOS TEST_CLK input • Output frequency range: 62.5MHz to 350MHz • VCO range: 250MHz to 700MHz • Parallel interface for programming counter and output dividers during power-up • Serial 3 wire interface • Cycle-to-cycle jitter: 23ps (typical) • Output skew: 16ps (typical) • Output duty cycle: 49% < odc < 51%, fout ≤ 125MHz • Full 3.3V or mixed 3.3V core, 2.5V operating supply • 0°C to 85°C ambient operating temperature • Lead-Free package available GENERAL DESCRIPTION The ICS84314 is a general purpose quad output frequency synthesizer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. When the device uses parallel loading, the M bits are programmable and the output divider is hard-wired for divide by 2 thus providing a frequency range of 125MHz to 350MHz. In serial programming mode, the M bits are programmable and the output divider can be set for either divide by 2 or divide by 4, providing a frequency range of 62.5MHz to 350MHz. The low cyclecycle jitter and broad frequency range of the ICS84314 make it an ideal clock generator for a variety of demanding applications which require high performance. ICS BLOCK DIAGRAM PIN ASSIGNMENT VCO_SEL nP_LOAD XTAL2 XTAL1 M3 M2 M1 M0 VCO_SEL 32 31 30 29 28 27 26 25 XTAL_SEL M4 TEST_CLK XTAL1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 24 23 22 TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR VCCO 0 M5 M6 OSC XTAL2 1 ÷ 16 M7 M8 VEE VCC ICS84314 21 20 19 18 17 PLL PHASE DETECTOR MR VCCO Q0 nQ0 0 1 VCO ÷M ÷2 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 ÷2 ÷4 Q1 nQ1 Q2 nQ2 Q3 nQ3 CONFIGURATION INTERFACE LOGIC 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 84314AY www.icst.com/products/hiperclocks.html 1 REV. C JANUARY 27, 2005 Integrated Circuit Systems, Inc. ICS84314 350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER nP_LOAD input is initially LOW. The data on inputs M0 through M8 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M bits can be hardwired to set the M divider to a specific default state that will automatically occur during power-up. In parallel mode, the N output divider is set to 2. In serial mode, the N output divider can be set for either ÷2 or ÷4. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fxtal x 2M fVCO = 16 The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 125 ≤ M ≤ 350. The frequency out is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1 N 16 N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS84314 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS84314 support two input modes to program the M divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the SERIAL LOADING S_CLOCK S.


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