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IP82C37A Dataheets PDF



Part Number IP82C37A
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description CMOS High Performance Programmable DMA Controller
Datasheet IP82C37A DatasheetIP82C37A Datasheet (PDF)

82C37A March 1997 CMOS High Performance Programmable DMA Controller Description The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersil’s advanced 2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A controller.

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82C37A March 1997 CMOS High Performance Programmable DMA Controller Description The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Intersil’s advanced 2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization feature. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation. The 82C37A is designed to be used with an external address latch, such as the 82C82, to demultiplex the most significant 8-bits of address. The 82C37A can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconfiguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process). Features • Compatible with the NMOS 8237A • Four Independent Maskable Channels with Autoinitialization Capability • Cascadable to any Number of Channels • High Speed Data Transfers: - Up to 4MBytes/sec with 8MHz Clock - Up to 6.25MBytes/sec with 12.5MHz Clock • Memory-to-Memory Transfers • Static CMOS Design Permits Low Power Operation - ICCSB = 10µA Maximum - ICCOP = 2mA/MHz Maximum • Fully TTL/CMOS Compatible • Internal Registers may be Read from Software Ordering Information PART NUMBER 5MHz CP82C37A-5 IP82C37A-5 CS82C37A-5 IS82C37A-5 CD82C37A-5 ID82C37A-5 MD82C37A-5/B 5962-9054301MQA MR82C37A-5/B 5962-9054301MXA 8MHz CP82C37A IP82C37A CS82C37A IS82C37A CD82C37A ID82C37A MD82C37A/B 5962-9054302MQA MR82C37A/B 5962-9054302MXA 12.5MHz CP82C37A-12 IP82C37A-12 CS82C37A-12 IS82C37A-12 CD82C37A-12 ID82C37A-12 MD82C37A-12/B 5962-9054303MQA MR82C37A-12/B 5962-9054303MXA SMD# 44 Pad CLCC SMD# -55oC to +125oC 40 Ld CERDIP 44 Ld PLCC PACKAGE 40 Ld PDIP TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC PKG. NO. E40.6 E40.6 N44.65 N44.65 F40.6 F40.6 F40.6 F40.6 J44.A J44.A CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 2967.1 4-192 82C37A Pinouts 82C37A (PDIP/CERDIP) TOP VIEW READY 82C37A (CLCC/PLCC) TOP VIEW MEMW MEMR EOP 39 A3 38 A2 37 A1 36 A0 35 VCC 34 DB0 33 DB1 32 DB2 31 DB3 30 DB4 29 NC 18 19 20 21 22 23 24 25 26 27 28 DREQ3 DREQ2 DREQ1 DREQ0 GND DB7 DB6 DACK3 DB5 DACK1 DACK0 IOW IOR IOR IOW MEMR MEMW NC READY HLDA ADSTB AEN HRQ CS CLK RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND) VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 A7 39 A6 38 A5 37 A4 36 EOP 35 A3 34 A2 33 A1 32 A0 31 VCC 30 DB0 29 DB1 28 DB2 27 DB3 26 DB4 25 DACK0 24 DACK1 23 DB5 22 DB6 21 DB7 NC 7 NC 8 HLDA 9 ADSTB 10 AEN 11 HRQ 12 CS 13 CLK 14 RESET 15 DACK2 16 NC 17 NC A7 A6 A5 6 5 4 3 2 1 44 43 42 41 40 Block Diagram EOP RESET CS READY CLK AEN ADSTB MEMR MEMW IOR IOW TIMING AND CONTROL DECREMENTOR TEMP WORD COUNT REG (16) 16-BIT BUS 16-BIT BUS READ BUFFER BASE ADDRESS (16) BASE WORD COUNT (16) READ WRITE BUFFER CURRENT ADDRESS (16) CURRENT WORD COUNT (16) OUTPUT BUFFER A4 - A7 INC/DECREMENTOR TEMP ADDRESS REG (16) IO BUFFER A0 - A3 A8 - A15 COMMAND CONTROL WRITE BUFFER 4 READ BUFFER D0 - D1 DREQ0 DREQ3 HLDA HRQ DACK0 DACK3 4 REQUEST (4) MODE (4 x 6) STATUS (8) TEMPORARY (8) 4-193 DB0 - DB7 PRIORITY ENCODER AND ROTATING PRIORITY LOGIC COMMAND (8) MASK (4) A4 INTERNAL DATA BUS IO BUFFER 82C37A Pin Description SYMBOL VCC PIN NUMBER 31 TYPE DESCRIPTION VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for decoupling. Ground I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the.


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